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<title>llvm-project.git/llvm/lib/CodeGen/MachineInstr.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>CodeGen: Remove TRI argument from getRegClass (#158225)</title>
<updated>2025-11-10T23:43:55+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-10T23:43:55+00:00</published>
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<content type='text'>
TargetInstrInfo now directly holds a reference to TargetRegisterInfo
and does not need TRI passed in anywhere.</content>
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<pre>
TargetInstrInfo now directly holds a reference to TargetRegisterInfo
and does not need TRI passed in anywhere.</pre>
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</content>
</entry>
<entry>
<title>CodeGen: More accurate mayAlias for instructions with multiple MMOs (#166211)</title>
<updated>2025-11-06T17:19:37+00:00</updated>
<author>
<name>Nicolai Hähnle</name>
<email>nicolai.haehnle@amd.com</email>
</author>
<published>2025-11-06T17:19:37+00:00</published>
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<content type='text'>
There can only be meaningful aliasing between the memory accesses of
different instructions if at least one of the accesses modifies memory.

This check is applied at the instruction-level earlier in the method.
This change merely extends the check on a per-MMO basis.

This affects a SystemZ test because PFD instructions are both mayLoad
and mayStore but may carry a load-only MMO which is now no longer
treated as aliasing loads. The PFD instructions are from llvm.prefetch
generated by loop-data-prefetch.</content>
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<pre>
There can only be meaningful aliasing between the memory accesses of
different instructions if at least one of the accesses modifies memory.

This check is applied at the instruction-level earlier in the method.
This change merely extends the check on a per-MMO basis.

This affects a SystemZ test because PFD instructions are both mayLoad
and mayStore but may carry a load-only MMO which is now no longer
treated as aliasing loads. The PFD instructions are from llvm.prefetch
generated by loop-data-prefetch.</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Extract copy-paste on PHI MachineInstr income removal. (#158634)</title>
<updated>2025-09-25T05:59:36+00:00</updated>
<author>
<name>Afanasyev Ivan</name>
<email>ivafanas@gmail.com</email>
</author>
<published>2025-09-25T05:59:36+00:00</published>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>CodeGen: Remove MachineFunction argument from getRegClass (#158188)</title>
<updated>2025-09-12T10:22:02+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-12T10:22:02+00:00</published>
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<id>7289f2cd0c371b2539faa628ec0eea58fa61892c</id>
<content type='text'>
This is a low level utility to parse the MCInstrInfo and should
not depend on the state of the function.</content>
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<pre>
This is a low level utility to parse the MCInstrInfo and should
not depend on the state of the function.</pre>
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</content>
</entry>
<entry>
<title>CodeGen: Remove MachineFunction argument from getPointerRegClass (#158185)</title>
<updated>2025-09-12T09:18:50+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-12T09:18:50+00:00</published>
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<id>2331fbb01978463a218d80883d29a003fdef6e14</id>
<content type='text'>
getPointerRegClass is a layering violation. Its primary purpose
is to determine how to interpret an MCInstrDesc's operands RegClass
fields. This should be context free, and only depend on the subtarget.
The model of this is also wrong, since this should be an
instruction / operand specific property, not a global pointer class.
Remove the the function argument to help stage removal of this hook
and avoid introducing any new obstacles to replacing it.

The remaining uses of the function were to get the subtarget, which
TargetRegisterInfo already belongs to. A few targets needed new
subtarget derived properties copied there.</content>
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<pre>
getPointerRegClass is a layering violation. Its primary purpose
is to determine how to interpret an MCInstrDesc's operands RegClass
fields. This should be context free, and only depend on the subtarget.
The model of this is also wrong, since this should be an
instruction / operand specific property, not a global pointer class.
Remove the the function argument to help stage removal of this hook
and avoid introducing any new obstacles to replacing it.

The remaining uses of the function were to get the subtarget, which
TargetRegisterInfo already belongs to. A few targets needed new
subtarget derived properties copied there.</pre>
</div>
</content>
</entry>
<entry>
<title>[GISel] Introduce MIFlags::InBounds (#150900)</title>
<updated>2025-07-30T11:01:23+00:00</updated>
<author>
<name>Fabian Ritter</name>
<email>fabian.ritter@amd.com</email>
</author>
<published>2025-07-30T11:01:23+00:00</published>
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<content type='text'>
This flag applies to G_PTR_ADD instructions and indicates that the operation
implements an inbounds getelementptr operation, i.e., the pointer operand is in
bounds wrt. the allocated object it is based on, and the arithmetic does not
change that.

It is set when the IRTranslator lowers inbounds GEPs (currently only in some
cases, to be extended with a future PR), and in the
(build|materialize)ObjectPtrOffset functions.

Inbounds information is useful in ISel when we have instructions that perform
address computations whose intermediate steps must be in the same memory region
as the final result. A follow-up patch will start using it for AMDGPU's flat
memory instructions, where the immediate offset must not affect the memory
aperture of the address.

This is analogous to a concurrent effort in SDAG: #131862
(related: #140017, #141725).

For SWDEV-516125.</content>
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<pre>
This flag applies to G_PTR_ADD instructions and indicates that the operation
implements an inbounds getelementptr operation, i.e., the pointer operand is in
bounds wrt. the allocated object it is based on, and the arithmetic does not
change that.

It is set when the IRTranslator lowers inbounds GEPs (currently only in some
cases, to be extended with a future PR), and in the
(build|materialize)ObjectPtrOffset functions.

Inbounds information is useful in ISel when we have instructions that perform
address computations whose intermediate steps must be in the same memory region
as the final result. A follow-up patch will start using it for AMDGPU's flat
memory instructions, where the immediate offset must not affect the memory
aperture of the address.

This is analogous to a concurrent effort in SDAG: #131862
(related: #140017, #141725).

For SWDEV-516125.</pre>
</div>
</content>
</entry>
<entry>
<title>[NFC][LLVM][CodeGen] Refactor MachineInstr operand accessors (#137261)</title>
<updated>2025-05-01T14:45:22+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-05-01T14:45:22+00:00</published>
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<id>64f552cefacbb36ccb5f6df7b57f532bb63f0006</id>
<content type='text'>
- Change MachineInstr operand accessors to use `ArrayRef` internally to
slice the operand array into sub-arrays.
- Minor: remove unnecessary {} on `MachineInstrBuilder::add`.</content>
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<pre>
- Change MachineInstr operand accessors to use `ArrayRef` internally to
slice the operand array into sub-arrays.
- Minor: remove unnecessary {} on `MachineInstrBuilder::add`.</pre>
</div>
</content>
</entry>
<entry>
<title>[llvm] Call hash_combine_range with ranges (NFC) (#136511)</title>
<updated>2025-04-20T23:36:03+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-04-20T23:36:03+00:00</published>
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</content>
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<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Construct SmallVector with iterator ranges (NFC) (#136258)</title>
<updated>2025-04-18T17:26:48+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-04-18T17:26:48+00:00</published>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Prune headers and move code out of line for build efficiency, NFC (#135622)</title>
<updated>2025-04-15T05:23:18+00:00</updated>
<author>
<name>Reid Kleckner</name>
<email>rnk@google.com</email>
</author>
<published>2025-04-15T05:23:18+00:00</published>
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<content type='text'>
I noticed these destructors taking time with -ftime-trace and moved some
of them for minor build efficiency improvements.

The main impact of moving destructors out of line is that it avoids
requiring container fields containing other types from being complete,
i.e. one can have uptr&lt;T&gt; or vector&lt;T&gt; as a field with an incomplete
type T, and that means we can reduce transitive includes, as with
LegalizerInfo.h.

Move expensive getDebugOperandsForReg template out-of-line. The
std::function instantiation shows up in time trace even if you don't use
the function.</content>
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<pre>
I noticed these destructors taking time with -ftime-trace and moved some
of them for minor build efficiency improvements.

The main impact of moving destructors out of line is that it avoids
requiring container fields containing other types from being complete,
i.e. one can have uptr&lt;T&gt; or vector&lt;T&gt; as a field with an incomplete
type T, and that means we can reduce transitive includes, as with
LegalizerInfo.h.

Move expensive getDebugOperandsForReg template out-of-line. The
std::function instantiation shows up in time trace even if you don't use
the function.</pre>
</div>
</content>
</entry>
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