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<title>llvm-project.git/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[llvm] Call hash_combine_range with ranges (NFC) (#136511)</title>
<updated>2025-04-20T23:36:03+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-04-20T23:36:03+00:00</published>
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<entry>
<title>[MIRVRegNamerUtils] Use Register. NFC</title>
<updated>2025-03-07T06:51:05+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-03-07T06:21:54+00:00</published>
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<entry>
<title>Revert "[CodeGen] Remove static member function Register::isVirtualRegister. NFC (#127968)"</title>
<updated>2025-02-20T22:06:21+00:00</updated>
<author>
<name>Christopher Di Bella</name>
<email>cjdb@google.com</email>
</author>
<published>2025-02-20T22:02:22+00:00</published>
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This reverts commit ff99af7ea03b3be46bec7203bd2b74048d29a52a.
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This reverts commit ff99af7ea03b3be46bec7203bd2b74048d29a52a.
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<entry>
<title>[CodeGen] Remove static member function Register::isVirtualRegister. NFC (#127968)</title>
<updated>2025-02-20T16:35:50+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-02-20T16:35:50+00:00</published>
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Use nonstatic member instead. This requires explicit conversions, but
many will go away as we continue converting unsigned to Register.

In a few places where it was simple, I changed unsigned to Register.</content>
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Use nonstatic member instead. This requires explicit conversions, but
many will go away as we continue converting unsigned to Register.

In a few places where it was simple, I changed unsigned to Register.</pre>
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<entry>
<title>[CodeGen] Avoid repeated hash lookups (NFC) (#110074)</title>
<updated>2024-09-26T14:57:34+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-09-26T14:57:34+00:00</published>
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<entry>
<title>[CodeGen] Use LocationSize for MMO getSize (#84751)</title>
<updated>2024-03-17T18:15:56+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2024-03-17T18:15:56+00:00</published>
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<id>601e102bdb55e12a2f791e0d68fd6f81ffc21e21</id>
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This is part of #70452 that changes the type used for the external
interface of MMO to LocationSize as opposed to uint64_t. This means the
constructors take LocationSize, and convert ~UINT64_C(0) to
LocationSize::beforeOrAfter(). The getSize methods return a
LocationSize.

This allows us to be more precise with unknown sizes, not accidentally
treating them as unsigned values, and in the future should allow us to
add proper scalable vector support but none of that is included in this
patch. It should mostly be an NFC.

Global ISel is still expected to use the underlying LLT as it needs, and
are not expected to see unknown sizes for generic operations. Most of
the changes are hopefully fairly mechanical, adding a lot of getValue()
calls and protecting them with hasValue() where needed.</content>
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This is part of #70452 that changes the type used for the external
interface of MMO to LocationSize as opposed to uint64_t. This means the
constructors take LocationSize, and convert ~UINT64_C(0) to
LocationSize::beforeOrAfter(). The getSize methods return a
LocationSize.

This allows us to be more precise with unknown sizes, not accidentally
treating them as unsigned values, and in the future should allow us to
add proper scalable vector support but none of that is included in this
patch. It should mostly be an NFC.

Global ISel is still expected to use the underlying LLT as it needs, and
are not expected to see unknown sizes for generic operations. Most of
the changes are hopefully fairly mechanical, adding a lot of getValue()
calls and protecting them with hasValue() where needed.</pre>
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</entry>
<entry>
<title>[CodeGen] Use *{Set,Map}::contains (NFC)</title>
<updated>2023-03-14T15:07:42+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2023-03-14T15:07:42+00:00</published>
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</entry>
<entry>
<title>[CodeGen] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFC</title>
<updated>2023-01-13T22:38:08+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2023-01-13T22:38:08+00:00</published>
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<id>e72ca520bb4806d4003ef69698089fd83a5777cb</id>
<content type='text'>
Use isPhysical/isVirtual methods.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D141715
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Use isPhysical/isVirtual methods.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D141715
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</entry>
<entry>
<title>[DebugInfo][NFC] Add new MachineOperand type and change DBG_INSTR_REF syntax</title>
<updated>2023-01-06T18:03:48+00:00</updated>
<author>
<name>Stephen Tozer</name>
<email>Stephen.Tozer@Sony.com</email>
</author>
<published>2022-09-15T10:26:57+00:00</published>
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This patch makes two notable changes to the MIR debug info representation,
which result in different MIR output but identical final DWARF output (NFC
w.r.t. the full compilation). The two changes are:

  * The introduction of a new MachineOperand type, MO_DbgInstrRef, which
    consists of two unsigned numbers that are used to index an instruction
    and an output operand within that instruction, having a meaning
    identical to first two operands of the current DBG_INSTR_REF
    instruction. This operand is only used in DBG_INSTR_REF (see below).
  * A change in syntax for the DBG_INSTR_REF instruction, shuffling the
    operands to make it resemble DBG_VALUE_LIST instead of DBG_VALUE,
    and replacing the first two operands with a single MO_DbgInstrRef-type
    operand.

This patch is the first of a set that will allow DBG_INSTR_REF
instructions to refer to multiple machine locations in the same manner
as DBG_VALUE_LIST.

Reviewed By: jmorse

Differential Revision: https://reviews.llvm.org/D129372
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This patch makes two notable changes to the MIR debug info representation,
which result in different MIR output but identical final DWARF output (NFC
w.r.t. the full compilation). The two changes are:

  * The introduction of a new MachineOperand type, MO_DbgInstrRef, which
    consists of two unsigned numbers that are used to index an instruction
    and an output operand within that instruction, having a meaning
    identical to first two operands of the current DBG_INSTR_REF
    instruction. This operand is only used in DBG_INSTR_REF (see below).
  * A change in syntax for the DBG_INSTR_REF instruction, shuffling the
    operands to make it resemble DBG_VALUE_LIST instead of DBG_VALUE,
    and replacing the first two operands with a single MO_DbgInstrRef-type
    operand.

This patch is the first of a set that will allow DBG_INSTR_REF
instructions to refer to multiple machine locations in the same manner
as DBG_VALUE_LIST.

Reviewed By: jmorse

Differential Revision: https://reviews.llvm.org/D129372
</pre>
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</entry>
<entry>
<title>[MIRVRegNamer] Avoid opcode hash collision</title>
<updated>2022-11-02T13:53:12+00:00</updated>
<author>
<name>John Brawn</name>
<email>john.brawn@arm.com</email>
</author>
<published>2022-10-28T13:17:01+00:00</published>
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D121929 happens to cause CodeGen/MIR/AArch64/mirnamer.mir to fail due
to a hash collision caused by adding two extra opcodes. The collision
is only in the top 19 bits of the hashed opcode so fix this by just
using the whole hash (in fixed width hex for consistency) instead of
the top 5 decimal digits.

Differential Revision: https://reviews.llvm.org/D137155
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D121929 happens to cause CodeGen/MIR/AArch64/mirnamer.mir to fail due
to a hash collision caused by adding two extra opcodes. The collision
is only in the top 19 bits of the hashed opcode so fix this by just
using the whole hash (in fixed width hex for consistency) instead of
the top 5 decimal digits.

Differential Revision: https://reviews.llvm.org/D137155
</pre>
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