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<title>llvm-project.git/llvm/lib/CodeGen/MIRParser/MILexer.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[GISel] Introduce MIFlags::InBounds (#150900)</title>
<updated>2025-07-30T11:01:23+00:00</updated>
<author>
<name>Fabian Ritter</name>
<email>fabian.ritter@amd.com</email>
</author>
<published>2025-07-30T11:01:23+00:00</published>
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<id>ef6eaa045aaa20c8c01d35c02b6200b3be5d5bb4</id>
<content type='text'>
This flag applies to G_PTR_ADD instructions and indicates that the operation
implements an inbounds getelementptr operation, i.e., the pointer operand is in
bounds wrt. the allocated object it is based on, and the arithmetic does not
change that.

It is set when the IRTranslator lowers inbounds GEPs (currently only in some
cases, to be extended with a future PR), and in the
(build|materialize)ObjectPtrOffset functions.

Inbounds information is useful in ISel when we have instructions that perform
address computations whose intermediate steps must be in the same memory region
as the final result. A follow-up patch will start using it for AMDGPU's flat
memory instructions, where the immediate offset must not affect the memory
aperture of the address.

This is analogous to a concurrent effort in SDAG: #131862
(related: #140017, #141725).

For SWDEV-516125.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This flag applies to G_PTR_ADD instructions and indicates that the operation
implements an inbounds getelementptr operation, i.e., the pointer operand is in
bounds wrt. the allocated object it is based on, and the arithmetic does not
change that.

It is set when the IRTranslator lowers inbounds GEPs (currently only in some
cases, to be extended with a future PR), and in the
(build|materialize)ObjectPtrOffset functions.

Inbounds information is useful in ISel when we have instructions that perform
address computations whose intermediate steps must be in the same memory region
as the final result. A follow-up patch will start using it for AMDGPU's flat
memory instructions, where the immediate offset must not affect the memory
aperture of the address.

This is analogous to a concurrent effort in SDAG: #131862
(related: #140017, #141725).

For SWDEV-516125.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Add NoaliasAddrSpace to AAMDnodes (#149247)</title>
<updated>2025-07-29T02:10:06+00:00</updated>
<author>
<name>Shoreshen</name>
<email>372660931@qq.com</email>
</author>
<published>2025-07-29T02:10:06+00:00</published>
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<id>a5deb59dfef13cb5eb8e3defc7e94904ea132a34</id>
<content type='text'>
This is the following PR of
https://github.com/llvm/llvm-project/pull/136553 which calculate
NoaliasAddrSpace.

This PR carries the info calculated into MIR by adding it into AAMDnodes</content>
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<pre>
This is the following PR of
https://github.com/llvm/llvm-project/pull/136553 which calculate
NoaliasAddrSpace.

This PR carries the info calculated into MIR by adding it into AAMDnodes</pre>
</div>
</content>
</entry>
<entry>
<title>[MIRLexer][RISCV] Eat a space after the Machine comment (#115365)</title>
<updated>2024-11-11T19:48:31+00:00</updated>
<author>
<name>Michael Maitland</name>
<email>michaeltmaitland@gmail.com</email>
</author>
<published>2024-11-11T19:48:31+00:00</published>
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<id>2b58458225fb0f9cce6dabce7e4451f86c8c73a5</id>
<content type='text'>
The MIRPrinter emits ` :: ` at the start of a MMO. The MIRLexer eats all
the white space after the operand and before the `::` when there is no
comment. We need to eat the space after the comment to allow MIRLexer to
parse comments on a MMO.</content>
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<pre>
The MIRPrinter emits ` :: ` at the start of a MMO. The MIRLexer eats all
the white space after the operand and before the `::` when there is no
comment. We need to eat the space after the comment to allow MIRLexer to
parse comments on a MMO.</pre>
</div>
</content>
</entry>
<entry>
<title>[GlobalISel] Import samesign flag (#114267)</title>
<updated>2024-10-30T18:56:25+00:00</updated>
<author>
<name>Thorsten Schütt</name>
<email>schuett@gmail.com</email>
</author>
<published>2024-10-30T18:56:25+00:00</published>
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<id>b3bb6f18bb5b2b8756b585b80d46d13ab3636a18</id>
<content type='text'>
Credits: https://github.com/llvm/llvm-project/pull/111419

Fixes icmp-flags.mir

First attempt: https://github.com/llvm/llvm-project/pull/113090

Revert: https://github.com/llvm/llvm-project/pull/114256</content>
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<pre>
Credits: https://github.com/llvm/llvm-project/pull/111419

Fixes icmp-flags.mir

First attempt: https://github.com/llvm/llvm-project/pull/113090

Revert: https://github.com/llvm/llvm-project/pull/114256</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[GlobalISel] Import samesign flag" (#114256)</title>
<updated>2024-10-30T16:03:17+00:00</updated>
<author>
<name>Thorsten Schütt</name>
<email>schuett@gmail.com</email>
</author>
<published>2024-10-30T16:03:17+00:00</published>
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<id>4b028773b2c977eb8494a39e4b3fb2f114d1e2b5</id>
<content type='text'>
Reverts llvm/llvm-project#113090</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Reverts llvm/llvm-project#113090</pre>
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</content>
</entry>
<entry>
<title>[GlobalISel] Import samesign flag (#113090)</title>
<updated>2024-10-30T15:34:01+00:00</updated>
<author>
<name>Thorsten Schütt</name>
<email>schuett@gmail.com</email>
</author>
<published>2024-10-30T15:34:01+00:00</published>
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<id>72b115301d1c0d56f40f5030bb8d16f422ac211b</id>
<content type='text'>
Credits: https://github.com/llvm/llvm-project/pull/111419</content>
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<pre>
Credits: https://github.com/llvm/llvm-project/pull/111419</pre>
</div>
</content>
</entry>
<entry>
<title>[AArch64][Libunwind] Add Support for FEAT_PAuthLR DWARF Instruction (#112171)</title>
<updated>2024-10-28T08:22:38+00:00</updated>
<author>
<name>Jack Styles</name>
<email>jack.styles@arm.com</email>
</author>
<published>2024-10-28T08:22:38+00:00</published>
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<id>86f76c3b171f95fd0560339f2ad0f4449277cf8d</id>
<content type='text'>
As part of FEAT_PAuthLR, a new DWARF Frame Instruction was introduced,
`DW_CFA_AARCH64_negate_ra_state_with_pc`. This instructs Libunwind that
the PC has been used with the signing instruction. This change includes
three commits
- Libunwind support for the newly introduced DWARF Instruction
- CodeGen Support for the DWARF Instructions
- Reversing the changes made in #96377. Due to
`DW_CFA_AARCH64_negate_ra_state_with_pc`'s requirements to be placed
immediately after the signing instruction, this would mean the CFI
Instruction location was not consistent with the generated location when
not using FEAT_PAuthLR. The commit reverses the changes and makes the
location consistent across the different branch protection options.
While this does have a code size effect, this is a negligible one.

For the ABI information, see here:
https://github.com/ARM-software/abi-aa/blob/853286c7ab66048e4b819682ce17f567b77a0291/aadwarf64/aadwarf64.rst#id23</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
As part of FEAT_PAuthLR, a new DWARF Frame Instruction was introduced,
`DW_CFA_AARCH64_negate_ra_state_with_pc`. This instructs Libunwind that
the PC has been used with the signing instruction. This change includes
three commits
- Libunwind support for the newly introduced DWARF Instruction
- CodeGen Support for the DWARF Instructions
- Reversing the changes made in #96377. Due to
`DW_CFA_AARCH64_negate_ra_state_with_pc`'s requirements to be placed
immediately after the signing instruction, this would mean the CFI
Instruction location was not consistent with the generated location when
not using FEAT_PAuthLR. The commit reverses the changes and makes the
location consistent across the different branch protection options.
While this does have a code size effect, this is a negligible one.

For the ABI information, see here:
https://github.com/ARM-software/abi-aa/blob/853286c7ab66048e4b819682ce17f567b77a0291/aadwarf64/aadwarf64.rst#id23</pre>
</div>
</content>
</entry>
<entry>
<title>[LLVM][MIR] Support parsing bfloat immediates in MIR parser (#96010)</title>
<updated>2024-06-25T20:44:14+00:00</updated>
<author>
<name>Stephen Chou</name>
<email>stephenchouca@users.noreply.github.com</email>
</author>
<published>2024-06-25T20:44:14+00:00</published>
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<id>3c24eb39fb7e9c8b61992c86cb44d8cacc5853d2</id>
<content type='text'>
Adds support in MIR parser for parsing bfloat immediates, and adds a
test for this.</content>
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<pre>
Adds support in MIR parser for parsing bfloat immediates, and adds a
test for this.</pre>
</div>
</content>
</entry>
<entry>
<title>[GlobalIsel] Import GEP flags (#93850)</title>
<updated>2024-06-14T18:56:43+00:00</updated>
<author>
<name>Thorsten Schütt</name>
<email>schuett@gmail.com</email>
</author>
<published>2024-06-14T18:56:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=b1f9440fa9286638bb1fe72a14d220770d1987cc'/>
<id>b1f9440fa9286638bb1fe72a14d220770d1987cc</id>
<content type='text'>
https://github.com/llvm/llvm-project/pull/90824</content>
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<pre>
https://github.com/llvm/llvm-project/pull/90824</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Add nneg and disjoint flags (#86650)</title>
<updated>2024-03-26T17:44:34+00:00</updated>
<author>
<name>Thorsten Schütt</name>
<email>schuett@gmail.com</email>
</author>
<published>2024-03-26T17:44:34+00:00</published>
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<id>da6cc4a24ff8953d51f7dc2c4974e8fc9089d693</id>
<content type='text'>
MachineInstr learned the new flags.</content>
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<pre>
MachineInstr learned the new flags.</pre>
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</content>
</entry>
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