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<title>llvm-project.git/llvm/lib/CodeGen/LivePhysRegs.cpp, branch users/nico/python-1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[PowerPC] Deprecate uses of ISD::ADDC/ISD::ADDE/ISD::SUBC/ISD::SUBE  (#133155)</title>
<updated>2025-04-03T17:22:49+00:00</updated>
<author>
<name>zhijian lin</name>
<email>zhijian@ca.ibm.com</email>
</author>
<published>2025-04-03T17:22:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=1a540c3b8bcefaf6b36f261341ce55a1a24eca21'/>
<id>1a540c3b8bcefaf6b36f261341ce55a1a24eca21</id>
<content type='text'>
ISD::ADDC, ISD::ADDE, ISD::SUBC and ISD::SUBE are being deprecated,
using ISD::UADDO_CARRY,ISD::USUBO_CARRY instead. Lowering the UADDO,
UADDO_CARRY, USUBO, USUBO_CARRY in the patch.</content>
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<pre>
ISD::ADDC, ISD::ADDE, ISD::SUBC and ISD::SUBE are being deprecated,
using ISD::UADDO_CARRY,ISD::USUBO_CARRY instead. Lowering the UADDO,
UADDO_CARRY, USUBO, USUBO_CARRY in the patch.</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Use Register::id(). NFC</title>
<updated>2025-03-06T17:08:21+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-03-06T16:56:54+00:00</published>
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<entry>
<title>[LivePhysRegs] Use MCRegister instead of MCPhysReg in interface. NFC</title>
<updated>2025-03-06T17:07:53+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-03-06T16:56:36+00:00</published>
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<id>68b1fe86283bd8ea7356fa9cbc126fe56178ab2d</id>
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</pre>
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</entry>
<entry>
<title>[FrameLowering] Use MCRegister instead of Register in CalleeSavedInfo. NFC (#128095)</title>
<updated>2025-02-21T07:44:05+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-02-21T07:44:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=af64f0a6c2e26b3fd1979c1fa380136e5528c9b3'/>
<id>af64f0a6c2e26b3fd1979c1fa380136e5528c9b3</id>
<content type='text'>
Callee saved registers should always be phyiscal registers. They are
often passed directly to other functions that take MCRegister like
getMinimalPhysRegClass or TargetRegisterClass::contains.

Unfortunately, sometimes the MCRegister is compared to a Register which
gave an ambiguous comparison error when the MCRegister is on the LHS.
Adding a MCRegister==Register comparison operator created more ambiguous
comparison errors elsewhere. These cases were usually comparing against
a base or frame pointer register that is a physical register in a
Register. For those I added an explicit conversion of Register to
MCRegister to fix the error.</content>
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<pre>
Callee saved registers should always be phyiscal registers. They are
often passed directly to other functions that take MCRegister like
getMinimalPhysRegClass or TargetRegisterClass::contains.

Unfortunately, sometimes the MCRegister is compared to a Register which
gave an ambiguous comparison error when the MCRegister is on the LHS.
Adding a MCRegister==Register comparison operator created more ambiguous
comparison errors elsewhere. These cases were usually comparing against
a base or frame pointer register that is a physical register in a
Register. For those I added an explicit conversion of Register to
MCRegister to fix the error.</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Use MCRegister instead of MCPhysReg in RegisterMaskPair. NFC (#123688)</title>
<updated>2025-01-21T15:04:35+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-01-21T15:04:35+00:00</published>
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<id>f5f32cef617c0796a7d980a464786949cbf21227</id>
<content type='text'>
Update some other places to avoid implicit conversions this introduces,
but I probably missed some.</content>
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<pre>
Update some other places to avoid implicit conversions this introduces,
but I probably missed some.</pre>
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</entry>
<entry>
<title>[MC] Simplify uses of subregs/superregs. NFC.</title>
<updated>2023-04-18T13:14:07+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-04-18T13:12:14+00:00</published>
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<id>c30c5f0122243326f89c0f0e9e78118ff34ca9ed</id>
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<pre>
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<entry>
<title>[MC] Use subregs/superregs instead of MCSubRegIterator/MCSuperRegIterator. NFC.</title>
<updated>2023-04-18T12:29:41+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-04-17T20:09:19+00:00</published>
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<id>14bc3748109c73adde7350da60366149ae0d4c3a</id>
<content type='text'>
Differential Revision: https://reviews.llvm.org/D148613
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<pre>
Differential Revision: https://reviews.llvm.org/D148613
</pre>
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</content>
</entry>
<entry>
<title>[llvm] Use llvm::reverse (NFC)</title>
<updated>2021-11-07T02:31:18+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2021-11-07T02:31:18+00:00</published>
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<id>843d1eda18c3a7a700fe0858748e175727498d21</id>
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<entry>
<title>[CodeGen] Tweak coding style in LivePhysRegs::stepForward. NFC.</title>
<updated>2021-11-01T16:01:24+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2021-11-01T15:56:31+00:00</published>
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<id>b8016b626ec7095c7d57ebfffb2135dc5c3077b8</id>
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<pre>
</pre>
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</entry>
<entry>
<title>[IfCvt] Don't use pristine register for counting liveins for predicated instructions.</title>
<updated>2021-07-11T13:45:54+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2021-07-11T13:45:54+00:00</published>
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<id>dc0bbc9d891ab20850761d8d75acc6676754ce2d</id>
<content type='text'>
The test case here hits machine verifier problems. There are volatile
long loads that the results of do not get used, loading into two dead
registers. IfCvt will predicate them and as it does will add implicit
uses of the predicating registers due to thinking they are live in. As
nothing has used the register, the machine verifier disagrees that they
are really live and we end up with a failure.

The registers come from Pristine regs that LivePhysRegs counts as live.
This patch adds a addLiveInsNoPristines method to be used instead in
IfCvt, so that only really live in regs need to be added as implicit
operands.

Differential Revision: https://reviews.llvm.org/D90965
</content>
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<pre>
The test case here hits machine verifier problems. There are volatile
long loads that the results of do not get used, loading into two dead
registers. IfCvt will predicate them and as it does will add implicit
uses of the predicating registers due to thinking they are live in. As
nothing has used the register, the machine verifier disagrees that they
are really live and we end up with a failure.

The registers come from Pristine regs that LivePhysRegs counts as live.
This patch adds a addLiveInsNoPristines method to be used instead in
IfCvt, so that only really live in regs need to be added as implicit
operands.

Differential Revision: https://reviews.llvm.org/D90965
</pre>
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