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<title>llvm-project.git/llvm/lib/CodeGen/LiveIntervals.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[CodeGen] Introduce a VirtRegOrUnit class to hold virtual reg or physical reg unit. NFC (#123768)</title>
<updated>2025-01-25T02:30:28+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-01-25T02:30:28+00:00</published>
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<content type='text'>
LiveIntervals and MachineVerifier were previously using Register to
store this, but reg units are different than physical registers. One
important difference is that 0 is a valid reg unit number, but it is not
a valid phyiscal register.

This patch introduces a new VirtRegOrUnit class that is distinct from
Register. It can be be converted to/from a virtual Register or a
MCRegUnit. I've made all conversions explicit and used assertions to
check the validity.

I also fixed a place in MachineVerifier that was ignoring reg unit 0.</content>
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<pre>
LiveIntervals and MachineVerifier were previously using Register to
store this, but reg units are different than physical registers. One
important difference is that 0 is a valid reg unit number, but it is not
a valid phyiscal register.

This patch introduces a new VirtRegOrUnit class that is distinct from
Register. It can be be converted to/from a virtual Register or a
MCRegUnit. I've made all conversions explicit and used assertions to
check the validity.

I also fixed a place in MachineVerifier that was ignoring reg unit 0.</pre>
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<entry>
<title>[NewPM] LiveIntervals: Check dependencies for invalidation (#123563)</title>
<updated>2025-01-24T05:53:46+00:00</updated>
<author>
<name>Akshat Oke</name>
<email>Akshat.Oke@amd.com</email>
</author>
<published>2025-01-24T05:53:46+00:00</published>
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<entry>
<title>[CodeGen][PM] Initialize analyses with isAnalysis=true (#118779)</title>
<updated>2024-12-06T09:55:54+00:00</updated>
<author>
<name>Akshat Oke</name>
<email>Akshat.Oke@amd.com</email>
</author>
<published>2024-12-06T09:55:54+00:00</published>
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Analyses should be marked as analyses.

Otherwise they are prone to get ignored by the legacy analysis cache mechanism and get scheduled redundantly.</content>
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Analyses should be marked as analyses.

Otherwise they are prone to get ignored by the legacy analysis cache mechanism and get scheduled redundantly.</pre>
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<entry>
<title>[LiveIntervals] Ignore artificial regs when adding kill flags (#116963)</title>
<updated>2024-12-04T20:25:31+00:00</updated>
<author>
<name>Sander de Smalen</name>
<email>sander.desmalen@arm.com</email>
</author>
<published>2024-12-04T20:25:31+00:00</published>
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<content type='text'>
If parts of a physical register for a given liverange, as assigned by
the register allocator, can be used to store other values not
represented by this liverange, then `LiveIntervals::addKillFlags`
normally avoids adding a kill flag on the use of this register
when the value's liverange ends.

However, if all the other regunits are artificial, then we can
still safely add the kill flag, since those parts of the register
can never be accessed independently.</content>
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<pre>
If parts of a physical register for a given liverange, as assigned by
the register allocator, can be used to store other values not
represented by this liverange, then `LiveIntervals::addKillFlags`
normally avoids adding a kill flag on the use of this register
when the value's liverange ends.

However, if all the other regunits are artificial, then we can
still safely add the kill flag, since those parts of the register
can never be accessed independently.</pre>
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</entry>
<entry>
<title>Check hasOptSize() in shouldOptimizeForSize() (#112626)</title>
<updated>2024-10-28T16:45:03+00:00</updated>
<author>
<name>Ellis Hoag</name>
<email>ellis.sparky.hoag@gmail.com</email>
</author>
<published>2024-10-28T16:45:03+00:00</published>
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<entry>
<title>[regalloc][basic] Change spill weight for optsize funcs (#112960)</title>
<updated>2024-10-21T18:10:50+00:00</updated>
<author>
<name>Ellis Hoag</name>
<email>ellis.sparky.hoag@gmail.com</email>
</author>
<published>2024-10-21T18:10:50+00:00</published>
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<content type='text'>
Change the spill weight calculations for `optsize` functions to remove
the block frequency multiplier. For those functions, we do not want to
consider the runtime cost of spilling, only the codesize cost.

I built a large app with the basic and greedy (default) register
allocator enabled.

| Regalloc Type | Uncompressed Size Delta | Compressed Size Delta |
| - | - | - |
| Basic | -303.8 KiB (-0.23%) | -232.0 KiB (-0.39%) |
| Greedy | 159.1 KiB (0.12%) | 130.1 KiB (0.22%) |

Since I only saw a size win with the basic register allocator, I decided
to only change the behavior for that type.</content>
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<pre>
Change the spill weight calculations for `optsize` functions to remove
the block frequency multiplier. For those functions, we do not want to
consider the runtime cost of spilling, only the codesize cost.

I built a large app with the basic and greedy (default) register
allocator enabled.

| Regalloc Type | Uncompressed Size Delta | Compressed Size Delta |
| - | - | - |
| Basic | -303.8 KiB (-0.23%) | -232.0 KiB (-0.39%) |
| Greedy | 159.1 KiB (0.12%) | 130.1 KiB (0.22%) |

Since I only saw a size win with the basic register allocator, I decided
to only change the behavior for that type.</pre>
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</content>
</entry>
<entry>
<title>LiveInterval: Make verify functions return bool (#109672)</title>
<updated>2024-09-24T04:32:47+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2024-09-24T04:32:47+00:00</published>
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This will allow the MachineVerifier to check these properties
instead of just asserting</content>
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<pre>
This will allow the MachineVerifier to check these properties
instead of just asserting</pre>
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</entry>
<entry>
<title>[CodeGen] Construct SmallVector with ArrayRef (NFC) (#101841)</title>
<updated>2024-08-04T07:41:29+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-08-04T07:41:29+00:00</published>
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<entry>
<title>[CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)</title>
<updated>2024-07-10T11:34:48+00:00</updated>
<author>
<name>paperchalice</name>
<email>liujunchang97@outlook.com</email>
</author>
<published>2024-07-10T11:34:48+00:00</published>
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<content type='text'>
- Add `LiveIntervalsAnalysis`.
- Add `LiveIntervalsPrinterPass`.
- Use `LiveIntervalsWrapperPass` in legacy pass manager.
- Use `std::unique_ptr` instead of raw pointer for `LICalc`, so
destructor and default move constructor can handle it correctly.

This would be the last analysis required by `PHIElimination`.</content>
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<pre>
- Add `LiveIntervalsAnalysis`.
- Add `LiveIntervalsPrinterPass`.
- Use `LiveIntervalsWrapperPass` in legacy pass manager.
- Use `std::unique_ptr` instead of raw pointer for `LICalc`, so
destructor and default move constructor can handle it correctly.

This would be the last analysis required by `PHIElimination`.</pre>
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</entry>
<entry>
<title>[CodeGen] Use range-based for loops (NFC) (#98104)</title>
<updated>2024-07-10T07:10:48+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-07-10T07:10:48+00:00</published>
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