This changes `MCRegUnit` type from `unsigned` to `enum class : unsigned` and inserts necessary casts. The added `MCRegUnitToIndex` functor is used with `SparseSet`, `SparseMultiSet` and `IndexedMap` in a few places. `MCRegUnit` is opaque to users, so it didn't seem worth making it a full-fledged class like `Register`. Static type checking has detected one issue in `PrologueEpilogueInserter.cpp`, where `BitVector` created for `MCRegister` is indexed by both `MCRegister` and `MCRegUnit`. The number of casts could be reduced by using `IndexedMap` in more places and/or adding a `BitVector` adaptor, but the number of casts *per file* is still small and `IndexedMap` has limitations, so it didn't seem worth the effort. Pull Request: https://github.com/llvm/llvm-project/pull/167943
Fixes #134424 Fixes #71023 Refer to the context of #71024, when RegisterCoalescer tries to merge `early-clobber %1:vr = PseudoVRGATHER_VI_M1 undef %1, ...`, JoinVals reports `CR_Replace` as the conflict with `undef` can be ignored. However, when pruning values, we need to remove any live ranges that overlap a `CR_Replace` resolution. `LiveIntervals::pruneValue` missed pruning the early-clobber part of the live ranges. This patch implements it by removing the ranges from live-in. I am not familiar with the RegisterCoalescer component. Any advice is appreciated. https://github.com/llvm/llvm-project/issues/156249 seems to be related, but not resolved with this patch. I am still investigating.
LiveIntervals and MachineVerifier were previously using Register to store this, but reg units are different than physical registers. One important difference is that 0 is a valid reg unit number, but it is not a valid phyiscal register. This patch introduces a new VirtRegOrUnit class that is distinct from Register. It can be be converted to/from a virtual Register or a MCRegUnit. I've made all conversions explicit and used assertions to check the validity. I also fixed a place in MachineVerifier that was ignoring reg unit 0.
Analyses should be marked as analyses. Otherwise they are prone to get ignored by the legacy analysis cache mechanism and get scheduled redundantly.
If parts of a physical register for a given liverange, as assigned by the register allocator, can be used to store other values not represented by this liverange, then `LiveIntervals::addKillFlags` normally avoids adding a kill flag on the use of this register when the value's liverange ends. However, if all the other regunits are artificial, then we can still safely add the kill flag, since those parts of the register can never be accessed independently.