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<title>llvm-project.git/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp, branch users/mingmingl-llvm/section-prefix</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[LiveDebugValues][NFC] Remove TargetPassConfig from LDVImpl (#131562)</title>
<updated>2025-03-18T05:34:54+00:00</updated>
<author>
<name>Akshat Oke</name>
<email>Akshat.Oke@amd.com</email>
</author>
<published>2025-03-18T05:34:54+00:00</published>
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TPC is only used to access the option `ShouldEmitDebugEntryValues`.</content>
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TPC is only used to access the option `ShouldEmitDebugEntryValues`.</pre>
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</entry>
<entry>
<title>[CodeGen] Avoid repeated hash lookups (NFC) (#129465)</title>
<updated>2025-03-03T15:27:16+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-03-03T15:27:16+00:00</published>
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<entry>
<title>[CodeGen] Remove some implict conversions of MCRegister to unsigned by using(). NFC</title>
<updated>2025-01-19T21:18:04+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-01-19T07:36:56+00:00</published>
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<content type='text'>
Many of these are indexing BitVectors or something where we can't
using MCRegister and need the register number.
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<pre>
Many of these are indexing BitVectors or something where we can't
using MCRegister and need the register number.
</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Remove unused includes (NFC) (#115996)</title>
<updated>2024-11-13T07:15:06+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-11-13T07:15:06+00:00</published>
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Identified with misc-include-cleaner.</content>
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Identified with misc-include-cleaner.</pre>
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</entry>
<entry>
<title>[LiveDebugValues][NVPTX]VarLocBasedImpl handle vregs, enable for NVPTX (#111456)</title>
<updated>2024-10-09T01:38:47+00:00</updated>
<author>
<name>William G Hatch</name>
<email>william@hatch.uno</email>
</author>
<published>2024-10-09T01:38:47+00:00</published>
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<id>181840459d2c8841ab8a564d4fbac6efc65e0fa9</id>
<content type='text'>
This patch handles virtual registers in the VarLocBasedImpl of the
LiveDebugVariables pass, allowing it to be used on architectures that
depend on virtual registers in debugging, like NVPTX. It enables the
pass for NVPTX.</content>
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<pre>
This patch handles virtual registers in the VarLocBasedImpl of the
LiveDebugVariables pass, allowing it to be used on architectures that
depend on virtual registers in debugging, like NVPTX. It enables the
pass for NVPTX.</pre>
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</content>
</entry>
<entry>
<title>[LiveDebugValues] Avoid repeated hash lookups (NFC) (#109509)</title>
<updated>2024-09-21T16:11:19+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-09-21T16:11:19+00:00</published>
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<entry>
<title>[CodeGen] Update a few places that were passing Register to raw_ostream::operator&lt;&lt; (#106877)</title>
<updated>2024-09-02T07:19:19+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2024-09-02T07:19:19+00:00</published>
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<id>cd3667d1dbc9c1db05aaf3cd5b39f33b143bd8b5</id>
<content type='text'>
These would implicitly cast the register to `unsigned`. Switch most of
them to use printReg will give a more readable output. Change some
others to use Register::id() so we can eventually remove the implicit
cast to `unsigned`.</content>
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<pre>
These would implicitly cast the register to `unsigned`. Switch most of
them to use printReg will give a more readable output. Change some
others to use Register::id() so we can eventually remove the implicit
cast to `unsigned`.</pre>
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</content>
</entry>
<entry>
<title>[llvm] Use range-based for loops (NFC) (#105861)</title>
<updated>2024-08-23T23:56:27+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-08-23T23:56:27+00:00</published>
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</pre>
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<entry>
<title>Fix typo "indicies" (#92232)</title>
<updated>2024-05-15T12:10:16+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-05-15T12:10:16+00:00</published>
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<id>1650f1b3d7f97ca95eb930984e74bdfd91b02b4e</id>
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</pre>
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<entry>
<title> [AArch64] ORRWrs is copy instruction when there's no implicit def of the X register (#75184)</title>
<updated>2023-12-14T11:19:55+00:00</updated>
<author>
<name>DianQK</name>
<email>dianqk@dianqk.net</email>
</author>
<published>2023-12-14T11:19:55+00:00</published>
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<content type='text'>
Follows
https://github.com/llvm/llvm-project/pull/74682#issuecomment-1850268782.
Fixes #74680.</content>
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Follows
https://github.com/llvm/llvm-project/pull/74682#issuecomment-1850268782.
Fixes #74680.</pre>
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