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<title>llvm-project.git/llvm/lib/CodeGen/InitUndef.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[CodeGen] Use non-static Register::virtRegIndex() instead of static Register::virtReg2Index. NFC (#125031)</title>
<updated>2025-01-30T08:14:08+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-01-30T08:14:08+00:00</published>
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<id>473953a15fcf68f2a213e2fed7b47a2a690baff2</id>
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These are the the ones where we already had a Register object being
used. Some places are still using unsigned which I did not convert.</content>
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<pre>
These are the the ones where we already had a Register object being
used. Some places are still using unsigned which I did not convert.</pre>
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<entry>
<title>[CodeGen] Remove unused argument from getCoveringSubRegIndexes. NFC. (#122884)</title>
<updated>2025-01-14T12:59:31+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2025-01-14T12:59:31+00:00</published>
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<pre>
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<entry>
<title>Reland "[InitUndef] handleSubReg should skip artificial subregs. (#116248)"</title>
<updated>2024-11-28T09:56:11+00:00</updated>
<author>
<name>Sander de Smalen</name>
<email>sander.desmalen@arm.com</email>
</author>
<published>2024-11-27T09:19:40+00:00</published>
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<id>61653f8e39666ea974561fd9ddccd7d473852fad</id>
<content type='text'>
This patch can now reland after 318c69de52b6 relanded #114827.

This reverts commit 1683f84d289348ba6879635c4161979204f75230.
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<pre>
This patch can now reland after 318c69de52b6 relanded #114827.

This reverts commit 1683f84d289348ba6879635c4161979204f75230.
</pre>
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</entry>
<entry>
<title>Revert "[InitUndef] handleSubReg should skip artificial subregs. (#116248)" (#117365)</title>
<updated>2024-11-22T19:24:48+00:00</updated>
<author>
<name>Vitaly Buka</name>
<email>vitalybuka@google.com</email>
</author>
<published>2024-11-22T19:24:48+00:00</published>
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<id>1683f84d289348ba6879635c4161979204f75230</id>
<content type='text'>
Maybe not needed but to avoid conflicts with #117307
Without revert of this one, but reverting #117307, the
regenerated init-undef.mir became empty.

This reverts commit be15fd5085680cc5ed9ec4f4f2258b504cdd55db.</content>
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<pre>
Maybe not needed but to avoid conflicts with #117307
Without revert of this one, but reverting #117307, the
regenerated init-undef.mir became empty.

This reverts commit be15fd5085680cc5ed9ec4f4f2258b504cdd55db.</pre>
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</entry>
<entry>
<title>[InitUndef] handleSubReg should skip artificial subregs. (#116248)</title>
<updated>2024-11-14T17:06:40+00:00</updated>
<author>
<name>Sander de Smalen</name>
<email>sander.desmalen@arm.com</email>
</author>
<published>2024-11-14T17:06:40+00:00</published>
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<id>be15fd5085680cc5ed9ec4f4f2258b504cdd55db</id>
<content type='text'>
When enabling subreg liveness tracking for AArch64, this pass fails
because it tries to get the register class for the artificial subreg
`sub_32_hi` of a 64-bit GPR. It tries to create an INIT_UNDEF
instruction for the top 32-bits of the 64-bit GPR, which are not
directly addressable, so getSubRegisterClass() returns a nullptr,
crashing this pass.

It should instead just avoid trying to create the INIT_UNDEF
instruction.</content>
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<pre>
When enabling subreg liveness tracking for AArch64, this pass fails
because it tries to get the register class for the artificial subreg
`sub_32_hi` of a 64-bit GPR. It tries to create an INIT_UNDEF
instruction for the top 32-bits of the 64-bit GPR, which are not
directly addressable, so getSubRegisterClass() returns a nullptr,
crashing this pass.

It should instead just avoid trying to create the INIT_UNDEF
instruction.</pre>
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</content>
</entry>
<entry>
<title>[InitUndef] Also handle inline asm (#108951)</title>
<updated>2024-09-19T07:59:36+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2024-09-19T07:59:36+00:00</published>
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<id>7183771834d9035ffbedd8f1ff9233b16722b986</id>
<content type='text'>
InitUndef should also handle early-clobber / undef conflicts in inline
asm operands. Do this by iterating over all_defs() instead of defs().

The newly added ARM test was generating an "unpredictable STXP instruction,
status is also a source" error prior to this change.

Fixes https://github.com/llvm/llvm-project/issues/106380.</content>
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<pre>
InitUndef should also handle early-clobber / undef conflicts in inline
asm operands. Do this by iterating over all_defs() instead of defs().

The newly added ARM test was generating an "unpredictable STXP instruction,
status is also a source" error prior to this change.

Fixes https://github.com/llvm/llvm-project/issues/106380.</pre>
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</entry>
<entry>
<title>[InitUndef] Enable the InitUndef pass on non-AMDGPU targets (#108353)</title>
<updated>2024-09-16T07:48:25+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2024-09-16T07:48:25+00:00</published>
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<id>dfa54298ff6d6e420a1a5b74c070912409713589</id>
<content type='text'>
The InitUndef pass works around a register allocation issue, where undef
operands can be allocated to the same register as early-clobber result
operands. This may lead to ISA constraint violations, where certain
input and output registers are not allowed to overlap.

Originally this pass was implemented for RISCV, and then extended to ARM
in #77770. I've since removed the target-specific parts of the pass in
#106744 and #107885. This PR reduces the pass to use a single
requiresDisjointEarlyClobberAndUndef() target hook and enables it by
default. The hook is disabled for AMDGPU, because overlapping
early-clobber and undef operands are known to be safe for that target,
and we get significant codegen diffs otherwise.

The motivating case is the one in arm64-ldxr-stxr.ll, where we were
previously incorrectly allocating a stxp input and output to the same
register.</content>
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<pre>
The InitUndef pass works around a register allocation issue, where undef
operands can be allocated to the same register as early-clobber result
operands. This may lead to ISA constraint violations, where certain
input and output registers are not allowed to overlap.

Originally this pass was implemented for RISCV, and then extended to ARM
in #77770. I've since removed the target-specific parts of the pass in
#106744 and #107885. This PR reduces the pass to use a single
requiresDisjointEarlyClobberAndUndef() target hook and enables it by
default. The hook is disabled for AMDGPU, because overlapping
early-clobber and undef operands are known to be safe for that target,
and we get significant codegen diffs otherwise.

The motivating case is the one in arm64-ldxr-stxr.ll, where we were
previously incorrectly allocating a stxp input and output to the same
register.</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Clear InitUndef pass new register cache between pass runs (#90967)</title>
<updated>2024-09-12T13:01:55+00:00</updated>
<author>
<name>Joe Faulls</name>
<email>67795994+joe-img@users.noreply.github.com</email>
</author>
<published>2024-09-12T13:01:55+00:00</published>
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<content type='text'>
Multiple invocations of the pass could interfere with eachother,
preventing some undefs being initialised.

I found it very difficult to create a unit test for this due to it being
dependent on particular allocations of a previous function. However, the
bug can be observed here: https://godbolt.org/z/7xnMo41Gv with the
creation of the illegal instruction `vnsrl.wi v9, v8, 0`</content>
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<pre>
Multiple invocations of the pass could interfere with eachother,
preventing some undefs being initialised.

I found it very difficult to create a unit test for this due to it being
dependent on particular allocations of a previous function. However, the
bug can be observed here: https://godbolt.org/z/7xnMo41Gv with the
creation of the illegal instruction `vnsrl.wi v9, v8, 0`</pre>
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</content>
</entry>
<entry>
<title>[InitUndef] Only compute DeadLaneDetector if subreg liveness enabled (NFC) (#108279)</title>
<updated>2024-09-12T07:00:47+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2024-09-12T07:00:47+00:00</published>
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<id>e2723c2a8af69677d68e9c11a394f08e6c205153</id>
<content type='text'>
InitUndef currently always computes DeadLaneDetector, but only actually
uses it if subreg liveness is enabled for the target. Make the
calculation optional to avoid an unnecessary compile-time impact for
targets that don't enable subreg liveness.</content>
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<pre>
InitUndef currently always computes DeadLaneDetector, but only actually
uses it if subreg liveness is enabled for the target. Make the
calculation optional to avoid an unnecessary compile-time impact for
targets that don't enable subreg liveness.</pre>
</div>
</content>
</entry>
<entry>
<title>[InitUndef] Don't use largest super class (#107885)</title>
<updated>2024-09-11T07:36:20+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2024-09-11T07:36:20+00:00</published>
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<id>1e3a24d2e4eb63c17b962161ae6588d1b2c178f8</id>
<content type='text'>
The InitUndef pass currently uses the getLargestSuperClass() hook (which
is only used by that pass) to chose the register to initialize. This was done
to reduce the number of undef init pseudos needed, e.g. so that the vrnov0
regclass would use the same pseudo as v0. After #106744 we use a single
generic pseudo, so this is no longer necessary.</content>
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<pre>
The InitUndef pass currently uses the getLargestSuperClass() hook (which
is only used by that pass) to chose the register to initialize. This was done
to reduce the number of undef init pseudos needed, e.g. so that the vrnov0
regclass would use the same pseudo as v0. After #106744 we use a single
generic pseudo, so this is no longer necessary.</pre>
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