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<title>llvm-project.git/llvm/lib/CodeGen/GlobalISel/Utils.cpp, branch users/nico/python-2</title>
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<entry>
<title>GlobalISel: Replace use of report_fatal_error (#145866)</title>
<updated>2025-06-27T12:16:23+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-06-27T12:16:23+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>[AArch64] Skip storing of stack arguments when lowering tail calls (#126735)</title>
<updated>2025-06-06T08:26:24+00:00</updated>
<author>
<name>Guy David</name>
<email>49722543+guy-david@users.noreply.github.com</email>
</author>
<published>2025-06-06T08:26:24+00:00</published>
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<id>4d4b7cc69e3e633aa7c068cca93a3d4beba8615c</id>
<content type='text'>
This issue starts in the selection DAG and causes the backend to emit
the following for a trivial tail call:
```
ldr w8, [sp]
str w8, [sp]
b func
```

I'm not too sure that checking for immutability of a specific stack
object is a good enough of a gurantee, because as soon a tail-call is
done lowering,`setHasTailCall()` is called and in that case perhaps a
pass is allowed to change the value of the object in-memory?

This can be extended to the ARM backend as well.
Removed the `tailcall` keyword from a few other test assets, I'm
assuming their original intent was left intact.</content>
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<pre>
This issue starts in the selection DAG and causes the backend to emit
the following for a trivial tail call:
```
ldr w8, [sp]
str w8, [sp]
b func
```

I'm not too sure that checking for immutability of a specific stack
object is a good enough of a gurantee, because as soon a tail-call is
done lowering,`setHasTailCall()` is called and in that case perhaps a
pass is allowed to change the value of the object in-memory?

This can be extended to the ARM backend as well.
Removed the `tailcall` keyword from a few other test assets, I'm
assuming their original intent was left intact.</pre>
</div>
</content>
</entry>
<entry>
<title>[LLVM][CodeGen] Add convenience accessors for MachineFunctionProperties (#140002)</title>
<updated>2025-05-22T15:07:52+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-05-22T15:07:52+00:00</published>
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<id>1fdf02ad5a4ca155017eea22688365a20aab077c</id>
<content type='text'>
Add per-property has&lt;Prop&gt;/set&lt;Prop&gt;/reset&lt;Prop&gt; functions to
MachineFunctionProperties.</content>
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<pre>
Add per-property has&lt;Prop&gt;/set&lt;Prop&gt;/reset&lt;Prop&gt; functions to
MachineFunctionProperties.</pre>
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</content>
</entry>
<entry>
<title>[GlobalISel] Take the result size into account when const folding icmp (#134365)</title>
<updated>2025-05-05T17:01:53+00:00</updated>
<author>
<name>KRM7</name>
<email>rugasikrisztian@gmail.com</email>
</author>
<published>2025-05-05T17:01:53+00:00</published>
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<id>0926d94453096a37ec324a51d88ec203baedc3ea</id>
<content type='text'>
The current implementation always creates a 1 bit constant for the
result of the `G_ICMP`, which will cause issues if the destination
register size is larger than that. With asserts enabled, it will cause a
crash in `buildConstant`:
```
llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp:322: virtual MachineInstrBuilder llvm::MachineIRBuilder::buildConstant(const DstOp &amp;, const ConstantInt &amp;): Assertion `EltTy.getScalarSizeInBits() == Val.getBitWidth() &amp;&amp; "creating constant with the wrong size"' failed. 
```</content>
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<pre>
The current implementation always creates a 1 bit constant for the
result of the `G_ICMP`, which will cause issues if the destination
register size is larger than that. With asserts enabled, it will cause a
crash in `buildConstant`:
```
llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp:322: virtual MachineInstrBuilder llvm::MachineIRBuilder::buildConstant(const DstOp &amp;, const ConstantInt &amp;): Assertion `EltTy.getScalarSizeInBits() == Val.getBitWidth() &amp;&amp; "creating constant with the wrong size"' failed. 
```</pre>
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</content>
</entry>
<entry>
<title>Reapply "[LLVM][ISel][AArch64 Remove AArch64ISD::FCM##z nodes. (#135817)"</title>
<updated>2025-04-24T12:44:41+00:00</updated>
<author>
<name>Paul Walker</name>
<email>paul.walker@arm.com</email>
</author>
<published>2025-04-24T12:22:40+00:00</published>
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<id>d7f3c3129344b133859d89d962fcdd5058702f72</id>
<content type='text'>
This reverts commit 427b6448a3af009e57c0142d6d8af83318b45093.

Original patch has been updated to include a fix to esnure
AArch64InstructionSelector::emitConstantVector supports all the cases
where isBuildVectorAllOnes returns true.
</content>
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<pre>
This reverts commit 427b6448a3af009e57c0142d6d8af83318b45093.

Original patch has been updated to include a fix to esnure
AArch64InstructionSelector::emitConstantVector supports all the cases
where isBuildVectorAllOnes returns true.
</pre>
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</entry>
<entry>
<title>Revert "[LLVM][ISel][AArch64 Remove AArch64ISD::FCM##z nodes. (#135817)"</title>
<updated>2025-04-24T09:48:54+00:00</updated>
<author>
<name>Paul Walker</name>
<email>paul.walker@arm.com</email>
</author>
<published>2025-04-24T09:30:50+00:00</published>
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<id>427b6448a3af009e57c0142d6d8af83318b45093</id>
<content type='text'>
This reverts commit 15d8b3cae9debc2bd7d27ca92ff599ba9fb30da5.
</content>
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<pre>
This reverts commit 15d8b3cae9debc2bd7d27ca92ff599ba9fb30da5.
</pre>
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</content>
</entry>
<entry>
<title>[LLVM][ISel][AArch64 Remove AArch64ISD::FCM##z nodes. (#135817)</title>
<updated>2025-04-23T10:29:42+00:00</updated>
<author>
<name>Paul Walker</name>
<email>paul.walker@arm.com</email>
</author>
<published>2025-04-23T10:29:42+00:00</published>
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<id>15d8b3cae9debc2bd7d27ca92ff599ba9fb30da5</id>
<content type='text'>
We can easily select compare-to-zero instructions without dedicated
nodes. The test changes show opportunities that were previous missed
because of the redundant complexity.</content>
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<pre>
We can easily select compare-to-zero instructions without dedicated
nodes. The test changes show opportunities that were previous missed
because of the redundant complexity.</pre>
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</content>
</entry>
<entry>
<title>[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)</title>
<updated>2025-03-29T10:51:29+00:00</updated>
<author>
<name>Tim Gymnich</name>
<email>tim@gymni.ch</email>
</author>
<published>2025-03-29T10:51:29+00:00</published>
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<id>1d0005a69ac812ea0ff069052daf4c2ea0242a48</id>
<content type='text'>
- rename `GISelKnownBits` to `GISelValueTracking` to analyze more than
just `KnownBits` in the future</content>
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<pre>
- rename `GISelKnownBits` to `GISelValueTracking` to analyze more than
just `KnownBits` in the future</pre>
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</content>
</entry>
<entry>
<title>[GISel] Combine `(neg (min/max x, (neg x)))` into `(max/min x, (neg x))` (#120998)</title>
<updated>2025-01-03T00:29:34+00:00</updated>
<author>
<name>Min-Yih Hsu</name>
<email>min.hsu@sifive.com</email>
</author>
<published>2025-01-03T00:29:34+00:00</published>
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<id>3cac26f5419b68d37e1919001e1c46a765df294f</id>
<content type='text'>
This is the GISel version of #120666. Also supports both unsigned and
signed version of min &amp; max.</content>
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<pre>
This is the GISel version of #120666. Also supports both unsigned and
signed version of min &amp; max.</pre>
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</content>
</entry>
<entry>
<title>[GlobalIsel] [Utility] [NFC] Added isConstantOrConstantSplatVectorFP to handle float constants. (#120935)</title>
<updated>2024-12-26T13:27:19+00:00</updated>
<author>
<name>Vikash Gupta</name>
<email>Vikash.Gupta@amd.com</email>
</author>
<published>2024-12-26T13:27:19+00:00</published>
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<id>c21a3776c94eef46ea43192c6d0b8df6258b6489</id>
<content type='text'>
Needed for #120104</content>
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<pre>
Needed for #120104</pre>
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