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<title>llvm-project.git/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[GlobalISel] Remove dead code. (NFC) (#145811)</title>
<updated>2025-06-26T01:48:27+00:00</updated>
<author>
<name>Pete Chou</name>
<email>petechou@gmail.com</email>
</author>
<published>2025-06-26T01:48:27+00:00</published>
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<id>13e06403b4ed7eb2482893c3663761e7b5abbf63</id>
<content type='text'>
LegalizerHelper::lowerMemCpyFamily only execpts G_MEMCPY, G_MEMMOVE, and
G_MMSET.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
LegalizerHelper::lowerMemCpyFamily only execpts G_MEMCPY, G_MEMMOVE, and
G_MMSET.</pre>
</div>
</content>
</entry>
<entry>
<title>[X86][GlobalISel] Enable SINCOS with libcall mapping (#142438)</title>
<updated>2025-06-25T06:37:33+00:00</updated>
<author>
<name>JaydeepChauhan14</name>
<email>chauhan.jaydeep.ashwinbhai@intel.com</email>
</author>
<published>2025-06-25T06:37:33+00:00</published>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>PowerPC: Stop reporting memcpy as an alias of memmove on AIX (#143836)</title>
<updated>2025-06-23T13:15:37+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-06-23T13:15:37+00:00</published>
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<id>a65e0edd6ac522a21744fa51cef6593fd782dea4</id>
<content type='text'>
Instead of reporting ___memmove as an implementation of memcpy,
make it unavailable and let the lowering logic consider memmove as
a fallback path.

This avoids a special case 1:N mapping for libcall implementations.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Instead of reporting ___memmove as an implementation of memcpy,
make it unavailable and let the lowering logic consider memmove as
a fallback path.

This avoids a special case 1:N mapping for libcall implementations.</pre>
</div>
</content>
</entry>
<entry>
<title>CodeGen: Emit error if getRegisterByName fails (#145194)</title>
<updated>2025-06-23T07:33:35+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-06-23T07:33:35+00:00</published>
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<id>48155f93dd84919432e3276a143f8ef46c247b9a</id>
<content type='text'>
This avoids using report_fatal_error and standardizes the error
message in a subset of the error conditions.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This avoids using report_fatal_error and standardizes the error
message in a subset of the error conditions.</pre>
</div>
</content>
</entry>
<entry>
<title>[GlobalISel] Widen vector loads from aligned ptrs (#144309)</title>
<updated>2025-06-21T06:42:54+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2025-06-21T06:42:54+00:00</published>
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<id>437346378fd4d40af30e6969621a605cbd6215d1</id>
<content type='text'>
If the pointer is aligned to more than the size of the vector, we can
widen the load up to next power of 2 size, as SDAG performs.

Some of the v3 tests are currently worse - those should be addressed in
other issues.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
If the pointer is aligned to more than the size of the vector, we can
widen the load up to next power of 2 size, as SDAG performs.

Some of the v3 tests are currently worse - those should be addressed in
other issues.</pre>
</div>
</content>
</entry>
<entry>
<title>[GlobalISel] Split Legalizer debug ouput into paragraphs. NFC (#143427)</title>
<updated>2025-06-15T08:43:18+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2025-06-15T08:43:18+00:00</published>
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<id>89f692a24f6a13ae5cf9e37f91abe6f34c403258</id>
<content type='text'>
This helps keep the legalizer output easier to read, splitting each
instructions legalization into a separate block.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This helps keep the legalizer output easier to read, splitting each
instructions legalization into a separate block.</pre>
</div>
</content>
</entry>
<entry>
<title>[GlobalISel] support lowering of G_SHUFFLEVECTOR with pointer args (#141959)</title>
<updated>2025-06-05T16:13:51+00:00</updated>
<author>
<name>Stanley Gambarin</name>
<email>stanley.gambarin@intel.com</email>
</author>
<published>2025-06-05T16:13:51+00:00</published>
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<id>33974b41c7988204f94d156b3ad8c8e6d032e326</id>
<content type='text'>
</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>AMDGPU/GlobalISel: Start legalizing minimumnum and maximumnum (#140900)</title>
<updated>2025-05-21T15:00:45+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-05-21T15:00:45+00:00</published>
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<id>2e2bbcacf813de52f6e7f48dea67e26de1f1f99e</id>
<content type='text'>
This is the bare minimum to get the intrinsic to compile for AMDGPU,
and it's not optimal. We need to follow along closer with the existing
G_FMINNUM/G_FMAXNUM with custom lowering to handle the IEEE=0 case
better.

Just re-use the existing lowering for the old semantics for
G_FMINNUM/G_FMAXNUM. This does not change G_FMINNUM/G_FMAXNUM's
treatment,
nor try to handle the general expansion without an underlying min/max
variant (or with G_FMINIMUM/G_FMAXIMUM).</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This is the bare minimum to get the intrinsic to compile for AMDGPU,
and it's not optimal. We need to follow along closer with the existing
G_FMINNUM/G_FMAXNUM with custom lowering to handle the IEEE=0 case
better.

Just re-use the existing lowering for the old semantics for
G_FMINNUM/G_FMAXNUM. This does not change G_FMINNUM/G_FMAXNUM's
treatment,
nor try to handle the general expansion without an underlying min/max
variant (or with G_FMINIMUM/G_FMAXIMUM).</pre>
</div>
</content>
</entry>
<entry>
<title>[GISel][AArch64] Added more efficient lowering of Bitreverse (#139233)</title>
<updated>2025-05-13T10:21:50+00:00</updated>
<author>
<name>jyli0116</name>
<email>yu.li@arm.com</email>
</author>
<published>2025-05-13T10:21:50+00:00</published>
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<id>382ad6f2e7050c4134300fbbe275bdbc1ff5442c</id>
<content type='text'>
GlobalISel was previously inefficient in handling bitreverses of vector
types. This deals with i16, i32, i64 vector types and converts them into
i8 bitreverses and rev instructions.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
GlobalISel was previously inefficient in handling bitreverses of vector
types. This deals with i16, i32, i64 vector types and converts them into
i8 bitreverses and rev instructions.</pre>
</div>
</content>
</entry>
<entry>
<title>[GlobalISel][AArch64] Handles bitreverse to prevent falling back (#138150)</title>
<updated>2025-05-06T08:57:01+00:00</updated>
<author>
<name>jyli0116</name>
<email>yu.li@arm.com</email>
</author>
<published>2025-05-06T08:57:01+00:00</published>
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<id>fd800487382e2ee3944493d58a961b6f48290243</id>
<content type='text'>
Handles bitreverse for vector types which were previously falling back
onto Selection DAG. Includes 8-bit element vectors greater than 128 bits
and less than 64 bits: &lt;32 x i8&gt;, &lt;4 x i8&gt;, and odd vector types: &lt;9 x
i8&gt;.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Handles bitreverse for vector types which were previously falling back
onto Selection DAG. Includes 8-bit element vectors greater than 128 bits
and less than 64 bits: &lt;32 x i8&gt;, &lt;4 x i8&gt;, and odd vector types: &lt;9 x
i8&gt;.</pre>
</div>
</content>
</entry>
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