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<title>llvm-project.git/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[llvm] Use *Set::insert_range (NFC) (#133353)</title>
<updated>2025-03-28T03:44:20+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-03-28T03:44:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=673f4705a827aba52b991d446a90a1c0ca5641a5'/>
<id>673f4705a827aba52b991d446a90a1c0ca5641a5</id>
<content type='text'>
We can use *Set::insert_range to collapse:

  for (auto Elem : Range)
    Set.insert(E.first);

down to:

  Set.insert_range(llvm::make_first_range(Range));

In some cases, we can further fold that into the set declaration.</content>
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<pre>
We can use *Set::insert_range to collapse:

  for (auto Elem : Range)
    Set.insert(E.first);

down to:

  Set.insert_range(llvm::make_first_range(Range));

In some cases, we can further fold that into the set declaration.</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Use Register or MCRegister. NFC</title>
<updated>2025-03-06T17:08:21+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-03-06T16:56:47+00:00</published>
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<pre>
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</entry>
<entry>
<title>[CodeGen][NewPM] Port "FixupStatepointCallerSaved" pass to NPM (#129541)</title>
<updated>2025-03-04T10:17:43+00:00</updated>
<author>
<name>Vikram Hegde</name>
<email>115221833+vikramRH@users.noreply.github.com</email>
</author>
<published>2025-03-04T10:17:43+00:00</published>
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</entry>
<entry>
<title>[CodeGen] Use Register::id() to avoid implicit cast. NFC</title>
<updated>2025-03-03T06:33:26+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-03-03T04:48:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=13cce8c0bcf0f2e5d02f863fcbee47e3d7956eca'/>
<id>13cce8c0bcf0f2e5d02f863fcbee47e3d7956eca</id>
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<entry>
<title>[CodeGen] Avoid repeated hash lookups (NFC) (#128126)</title>
<updated>2025-02-21T19:07:07+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-02-21T19:07:07+00:00</published>
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<id>b0443507014273bb95eb90af0f9859a8fa3111c9</id>
<content type='text'>
This patch eliminates repeated hash lookups at three levels:

- RegToSlotIdx  of DenseMap
- Reloads       of DenseMap
- Reloads[MBB]  of SmallSet</content>
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This patch eliminates repeated hash lookups at three levels:

- RegToSlotIdx  of DenseMap
- Reloads       of DenseMap
- Reloads[MBB]  of SmallSet</pre>
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</entry>
<entry>
<title>[CodeGen] Avoid repeated hash lookups (NFC) (#123500)</title>
<updated>2025-01-19T18:57:25+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-01-19T18:57:25+00:00</published>
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<id>3d15bfb40c14233a479439eb98f0318d1795b02a</id>
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</entry>
<entry>
<title>[Statepoint] Treat undef operands less specially (#119682)</title>
<updated>2024-12-17T05:59:46+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2024-12-17T05:59:46+00:00</published>
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<id>5e727e8bed5c57cbc804a2453bba1c2379084f27</id>
<content type='text'>
This reverts commit f7443905af1e06eaacda1e437fff8d54dc89c487.

This is to avoid an assertion if an undef operand appears in a
stackmap. This is important to avoid hitting verifier errors
when register allocation starts adding undefs in error scenarios.

Rather than trying to treat undef operands as special, leave them
alone and avoid producing an invalid spill. It would a bit more
precise to produce a spill of an undef register here, but that's not
exposed through the storeRegToStackSlot API.

https://reviews.llvm.org/D122605

This was an alternative to https://reviews.llvm.org/D122582</content>
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<pre>
This reverts commit f7443905af1e06eaacda1e437fff8d54dc89c487.

This is to avoid an assertion if an undef operand appears in a
stackmap. This is important to avoid hitting verifier errors
when register allocation starts adding undefs in error scenarios.

Rather than trying to treat undef operands as special, leave them
alone and avoid producing an invalid spill. It would a bit more
precise to produce a spill of an undef register here, but that's not
exposed through the storeRegToStackSlot API.

https://reviews.llvm.org/D122605

This was an alternative to https://reviews.llvm.org/D122582</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Make the parameter TRI required in some functions. (#85968)</title>
<updated>2024-04-24T13:24:14+00:00</updated>
<author>
<name>Xu Zhang</name>
<email>simonzgx@gmail.com</email>
</author>
<published>2024-04-24T13:24:14+00:00</published>
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<id>f6d431f208c0fa48827eac40e7acf788346a9967</id>
<content type='text'>
Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and  `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI  parameters, as shown in issue #82411.

Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`,  `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.

After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.</content>
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<pre>
Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and  `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI  parameters, as shown in issue #82411.

Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`,  `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.

After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.</pre>
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</entry>
<entry>
<title>[AMDGPU] RA inserted scalar instructions can be at the BB top (#72140)</title>
<updated>2023-11-16T05:00:03+00:00</updated>
<author>
<name>Christudasan Devadasan</name>
<email>christudasan.devadasan@amd.com</email>
</author>
<published>2023-11-16T05:00:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=ce7fd498ed91344c23f0864bbd5b84d65eaae3ef'/>
<id>ce7fd498ed91344c23f0864bbd5b84d65eaae3ef</id>
<content type='text'>
We adjust the insertion point at the BB top for spills/copies during RA
to ensure they are placed after the exec restore instructions required
for the divergent control flow execution. This is, however, required
only for the vector operations. The insertions for scalar registers can
still go to the BB top.</content>
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<pre>
We adjust the insertion point at the BB top for spills/copies during RA
to ensure they are placed after the exec restore instructions required
for the divergent control flow execution. This is, however, required
only for the vector operations. The insertions for scalar registers can
still go to the BB top.</pre>
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</content>
</entry>
<entry>
<title>[Statepoint] Use correct RegisterClass for spilling</title>
<updated>2023-07-20T13:00:00+00:00</updated>
<author>
<name>Danila Malyutin</name>
<email>dmalyutin@azul.com</email>
</author>
<published>2023-07-20T07:10:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=e1aa4e7b383e37442df6bb49f4f3db2069487765'/>
<id>e1aa4e7b383e37442df6bb49f4f3db2069487765</id>
<content type='text'>
Copy propagation might have changed the register class of the register

Differential Revision: https://reviews.llvm.org/D155792
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<pre>
Copy propagation might have changed the register class of the register

Differential Revision: https://reviews.llvm.org/D155792
</pre>
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