llvm-project.git/llvm/lib/CodeGen/CodeGen.cpp, branch users/ojhunt/ptrauth-additions Unnamed repository; edit this file 'description' to name the repository. [IR2Vec] Initial infrastructure for MIR2Vec (#161463) 2025-10-07T20:45:20+00:00 S. VenkataKeerthy 31350914+svkeerthy@users.noreply.github.com 2025-10-07T20:45:20+00:00 879f8616ef93b5f3732568aeabdade6af26094f7 This PR introduces the initial infrastructure and vocabulary necessary for generating embeddings for MIR (discussed briefly in the earlier IR2Vec RFC - https://discourse.llvm.org/t/rfc-enhancing-mlgo-inlining-with-ir2vec-embeddings). The MIR2Vec embeddings are useful in driving target specific optimizations that work on MIR like register allocation. (Tracking issue - #141817) 
This PR introduces the initial infrastructure and vocabulary necessary for generating embeddings for MIR (discussed briefly in the earlier IR2Vec RFC - https://discourse.llvm.org/t/rfc-enhancing-mlgo-inlining-with-ir2vec-embeddings).  The MIR2Vec embeddings are useful in driving target specific optimizations that work on MIR like register allocation.

(Tracking issue - #141817)
 [CodeGen][NewPM] Port `ReachingDefAnalysis` to new pass manager. (#159572) 2025-09-19T13:38:34+00:00 Mikhail Gudim mgudim@gmail.com 2025-09-19T13:38:34+00:00 562146499c391f72d3bed6d91a80d432af14db49 In this commit: (1) Added new pass manager support for `ReachingDefAnalysis`. (2) Added printer pass. (3) Make old pass manager use `ReachingDefInfoWrapperPass` 
In this commit:
  (1) Added new pass manager support for `ReachingDefAnalysis`.
  (2) Added printer pass.
  (3) Make old pass manager use `ReachingDefInfoWrapperPass`
 [CodeGen] Remove FinalizeMachineBundles pass (#149806) 2025-07-23T10:36:49+00:00 Jay Foad jay.foad@amd.com 2025-07-23T10:36:49+00:00 d449d3dc13daff388cbf6a7bb910e0511804eb84 Replace its only use in the AMDGPU R600 backend with a call to finalizeBundles. 
Replace its only use in the AMDGPU R600 backend with a call to
finalizeBundles.
 [CodeGen][NPM] Port ProcessImplicitDefs to NPM (#148110) 2025-07-16T07:53:27+00:00 Vikram Hegde 115221833+vikramRH@users.noreply.github.com 2025-07-16T07:53:27+00:00 4aa85cc3136e1b6d389ed0a9a109a17b1199a242 same as https://github.com/llvm/llvm-project/pull/138829 Co-authored-by : Oke, Akshat <[Akshat.Oke@amd.com](mailto:Akshat.Oke@amd.com)> 
same as https://github.com/llvm/llvm-project/pull/138829

Co-authored-by : Oke, Akshat
<[Akshat.Oke@amd.com](mailto:Akshat.Oke@amd.com)>
 [CodeGen][NewPM] Port "PostRAMachineSink" pass to NPM (#129690) 2025-07-10T07:40:46+00:00 Vikram Hegde 115221833+vikramRH@users.noreply.github.com 2025-07-10T07:40:46+00:00 fcd4a2fe7adfd0a58029583350692f3627d396e4 






[CodeGen][NPM] Port InitUndef to NPM (#138495)
2025-07-09T10:01:31+00:00

Akshat Oke
Akshat.Oke@amd.com

2025-07-09T10:01:31+00:00

b33d95fb8a873d1bd4d41323873e93d8c3cbd2a5












[CodeGen][NPM] Port VirtRegRewriter to NPM (#130564)
2025-04-30T08:40:46+00:00

Akshat Oke
Akshat.Oke@amd.com

2025-04-30T08:40:46+00:00

e91cbd4f299fd3f42928aff63f5d95f07be3f7fc












[CodeGen][NewPM] Port "ShrinkWrap" pass to NPM (#129880)
2025-04-30T07:41:17+00:00

Vikram Hegde
115221833+vikramRH@users.noreply.github.com

2025-04-30T07:41:17+00:00

53a8b8900397bd16167fe537d53c0c8d84911534












[CodeGen][NewPM] Port "PrologEpilogInserter" to NPM (#130550)
2025-04-29T07:43:45+00:00

Vikram Hegde
115221833+vikramRH@users.noreply.github.com

2025-04-29T07:43:45+00:00

86d8e8d9a617461eb4dae7b49e9a4a59a35024e7












[CodeGen][NPM] Port UnreachableMachineBlockElim to NPM (#136127)
2025-04-18T09:36:30+00:00

Akshat Oke
Akshat.Oke@amd.com

2025-04-18T09:36:30+00:00

31ddaef8d18d643ff4c343d03ddfe2edae7d22a2