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<title>llvm-project.git/llvm/lib/CodeGen/CalcSpillWeights.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[RegAlloc] Sort CopyHint by IsCSR (#131046)</title>
<updated>2025-04-14T13:58:46+00:00</updated>
<author>
<name>Michael Maitland</name>
<email>michaeltmaitland@gmail.com</email>
</author>
<published>2025-04-14T13:58:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=74e8f29f3138431abc9b393579733f3bbd0d85d8'/>
<id>74e8f29f3138431abc9b393579733f3bbd0d85d8</id>
<content type='text'>
`weightCalcHelper` is responsible for adding hints to MRI. Prior to this
PR, we fell back on register ID as the last tie breaker for sorting
hints. However, there is an opportunity to add an additional sorting
characteristic: whether or not a register is a callee-saved-register.

I thought of this idea because I saw that `AllocationOrder::create`
calls `RegisterClassInfo::getOrder`, which returns a list of registers
such that the registers which alias callee-saved-registers come last.
From this, I conclude that the register allocator prefers an order such
that callee-saved-registers are allocated after
non-callee-saved-registers to avoid having to spill the CSR.

This sorting characteristic occurs only as a tie breaker to the Weight
calculation. This is a good idea since the weight calculation is pretty
complex and I'm sure it is a pretty stable metric. I think its pretty
reasonable to agree that whether a register is callee-saved or not is a
better tie breaker than register ID. I think this is evident by the test
diff, since the changes all seem to have no impact or improve the
register allocation.</content>
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<pre>
`weightCalcHelper` is responsible for adding hints to MRI. Prior to this
PR, we fell back on register ID as the last tie breaker for sorting
hints. However, there is an opportunity to add an additional sorting
characteristic: whether or not a register is a callee-saved-register.

I thought of this idea because I saw that `AllocationOrder::create`
calls `RegisterClassInfo::getOrder`, which returns a list of registers
such that the registers which alias callee-saved-registers come last.
From this, I conclude that the register allocator prefers an order such
that callee-saved-registers are allocated after
non-callee-saved-registers to avoid having to spill the CSR.

This sorting characteristic occurs only as a tie breaker to the Weight
calculation. This is a good idea since the weight calculation is pretty
complex and I'm sure it is a pretty stable metric. I think its pretty
reasonable to agree that whether a register is callee-saved or not is a
better tie breaker than register ID. I think this is evident by the test
diff, since the changes all seem to have no impact or improve the
register allocation.</pre>
</div>
</content>
</entry>
<entry>
<title>[RegAlloc] Scale the spill weight by target factor (#113675)</title>
<updated>2025-03-13T04:27:59+00:00</updated>
<author>
<name>Pengcheng Wang</name>
<email>wangpengcheng.pp@bytedance.com</email>
</author>
<published>2025-03-13T04:27:59+00:00</published>
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<id>08a3c532255d2af8722c32a7484a8648ac0ae2f5</id>
<content type='text'>
Currently, the spill weight is only determined by isDef/isUse and
block frequency. However, for registers with different register
classes, the costs of spilling them are different.

For example, for `LMUL&gt;1` registers (in which, several physical
registers compound a bigger logical register), the costs are larger
than `LMUL=1` case (in which, there is only one physical register).

To solve this problem, a new target hook `getSpillWeightScaleFactor`
is added. Targets can override the default factor (which is `1.0`)
according to the register class.

For RISC-V, the factors are set to the `RegClassWeight` which is
used to track register pressure. The values of `RegClassWeight`
happen to be the number of register units.

I believe all of the targets with compounded registers can benefit
from this change, but only RISC-V is customized in this patch since
it has widely been agreed to do so. The other targets need more
performance data to go further.

Partially fixes #113489.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Currently, the spill weight is only determined by isDef/isUse and
block frequency. However, for registers with different register
classes, the costs of spilling them are different.

For example, for `LMUL&gt;1` registers (in which, several physical
registers compound a bigger logical register), the costs are larger
than `LMUL=1` case (in which, there is only one physical register).

To solve this problem, a new target hook `getSpillWeightScaleFactor`
is added. Targets can override the default factor (which is `1.0`)
according to the register class.

For RISC-V, the factors are set to the `RegClassWeight` which is
used to track register pressure. The values of `RegClassWeight`
happen to be the number of register units.

I believe all of the targets with compounded registers can benefit
from this change, but only RISC-V is customized in this patch since
it has widely been agreed to do so. The other targets need more
performance data to go further.

Partially fixes #113489.</pre>
</div>
</content>
</entry>
<entry>
<title>[CalcSpillWeights] Use Register. NFC</title>
<updated>2025-03-03T07:46:17+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-03-03T06:54:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=9f8e148a6cdcdb8e89c284c2bc71e3ea28d2c5f1'/>
<id>9f8e148a6cdcdb8e89c284c2bc71e3ea28d2c5f1</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Remove unused includes (NFC) (#115996)</title>
<updated>2024-11-13T07:15:06+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-11-13T07:15:06+00:00</published>
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<id>735ab61ac828bd61398e6847d60e308fdf2b54ec</id>
<content type='text'>
Identified with misc-include-cleaner.</content>
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<pre>
Identified with misc-include-cleaner.</pre>
</div>
</content>
</entry>
<entry>
<title>[CalcSpillWeights] Simplify copy hint register collection. NFC. (#114236)</title>
<updated>2024-11-07T11:52:08+00:00</updated>
<author>
<name>Valery Pykhtin</name>
<email>valery.pykhtin@gmail.com</email>
</author>
<published>2024-11-07T11:52:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=9470945b6695cf526df9249c3787d225f95eaf03'/>
<id>9470945b6695cf526df9249c3787d225f95eaf03</id>
<content type='text'>
CopyHints set has been collecting duplicates of a register with
increasing weight and then deduplicated with HintedRegs set. Let's stop
collecting duplicates at the first place.</content>
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<pre>
CopyHints set has been collecting duplicates of a register with
increasing weight and then deduplicated with HintedRegs set. Let's stop
collecting duplicates at the first place.</pre>
</div>
</content>
</entry>
<entry>
<title>[regalloc][basic] Change spill weight for optsize funcs (#112960)</title>
<updated>2024-10-21T18:10:50+00:00</updated>
<author>
<name>Ellis Hoag</name>
<email>ellis.sparky.hoag@gmail.com</email>
</author>
<published>2024-10-21T18:10:50+00:00</published>
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<id>e6ada7162e25ab28f6e588fba23f0c11dd1238b5</id>
<content type='text'>
Change the spill weight calculations for `optsize` functions to remove
the block frequency multiplier. For those functions, we do not want to
consider the runtime cost of spilling, only the codesize cost.

I built a large app with the basic and greedy (default) register
allocator enabled.

| Regalloc Type | Uncompressed Size Delta | Compressed Size Delta |
| - | - | - |
| Basic | -303.8 KiB (-0.23%) | -232.0 KiB (-0.39%) |
| Greedy | 159.1 KiB (0.12%) | 130.1 KiB (0.22%) |

Since I only saw a size win with the basic register allocator, I decided
to only change the behavior for that type.</content>
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<pre>
Change the spill weight calculations for `optsize` functions to remove
the block frequency multiplier. For those functions, we do not want to
consider the runtime cost of spilling, only the codesize cost.

I built a large app with the basic and greedy (default) register
allocator enabled.

| Regalloc Type | Uncompressed Size Delta | Compressed Size Delta |
| - | - | - |
| Basic | -303.8 KiB (-0.23%) | -232.0 KiB (-0.39%) |
| Greedy | 159.1 KiB (0.12%) | 130.1 KiB (0.22%) |

Since I only saw a size win with the basic register allocator, I decided
to only change the behavior for that type.</pre>
</div>
</content>
</entry>
<entry>
<title>[NFC] Reapply 3f37c517f, SmallDenseMap speedups</title>
<updated>2024-09-26T09:49:29+00:00</updated>
<author>
<name>Jeremy Morse</name>
<email>jeremy.morse@sony.com</email>
</author>
<published>2024-09-26T08:47:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=056a3f4673a4f88d89e9bf00614355f671014ca5'/>
<id>056a3f4673a4f88d89e9bf00614355f671014ca5</id>
<content type='text'>
This time with 100% more building unit tests. Original commit message follows.

[NFC] Switch a number of DenseMaps to SmallDenseMaps for speedup (#109417)

If we use SmallDenseMaps instead of DenseMaps at these locations,
we get a substantial speedup because there's less spurious malloc
traffic. Discovered by instrumenting DenseMap with some accounting
code, then selecting sites where we'll get the most bang for our buck.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This time with 100% more building unit tests. Original commit message follows.

[NFC] Switch a number of DenseMaps to SmallDenseMaps for speedup (#109417)

If we use SmallDenseMaps instead of DenseMaps at these locations,
we get a substantial speedup because there's less spurious malloc
traffic. Discovered by instrumenting DenseMap with some accounting
code, then selecting sites where we'll get the most bang for our buck.
</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[NFC] Switch a number of DenseMaps to SmallDenseMaps for speedup (#109417)"</title>
<updated>2024-09-25T13:31:30+00:00</updated>
<author>
<name>Jeremy Morse</name>
<email>jeremy.morse@sony.com</email>
</author>
<published>2024-09-25T13:31:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=817e742ba55406688bf1f00557d24a60cfce962f'/>
<id>817e742ba55406688bf1f00557d24a60cfce962f</id>
<content type='text'>
This reverts commit 3f37c517fbc40531571f8b9f951a8610b4789cd6.

Lo and behold, I missed a unit test
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This reverts commit 3f37c517fbc40531571f8b9f951a8610b4789cd6.

Lo and behold, I missed a unit test
</pre>
</div>
</content>
</entry>
<entry>
<title>[NFC] Switch a number of DenseMaps to SmallDenseMaps for speedup (#109417)</title>
<updated>2024-09-25T13:22:23+00:00</updated>
<author>
<name>Jeremy Morse</name>
<email>jeremy.morse@sony.com</email>
</author>
<published>2024-09-25T13:22:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=3f37c517fbc40531571f8b9f951a8610b4789cd6'/>
<id>3f37c517fbc40531571f8b9f951a8610b4789cd6</id>
<content type='text'>
If we use SmallDenseMaps instead of DenseMaps at these locations,
we get a substantial speedup because there's less spurious malloc
traffic. Discovered by instrumenting DenseMap with some accounting
code, then selecting sites where we'll get the most bang for our buck.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
If we use SmallDenseMaps instead of DenseMaps at these locations,
we get a substantial speedup because there's less spurious malloc
traffic. Discovered by instrumenting DenseMap with some accounting
code, then selecting sites where we'll get the most bang for our buck.</pre>
</div>
</content>
</entry>
<entry>
<title>[CalcSpillWeights] Avoid x87 excess precision influencing weight result</title>
<updated>2024-07-26T18:47:33+00:00</updated>
<author>
<name>Dimitry Andric</name>
<email>dimitry@andric.com</email>
</author>
<published>2024-07-23T17:02:36+00:00</published>
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<id>c80c09f3e380a0a2b00b36bebf72f43271a564c1</id>
<content type='text'>
Fixes #99396

The result of `VirtRegAuxInfo::weightCalcHelper` can be influenced by
x87 excess precision, which can result in slightly different register
choices when the compiler is hosted on x86_64 or i386. This leads to
different object file output when cross-compiling to i386, or native.

Similar to 7af3432e22b0, we need to add a `volatile` qualifier to the
local `Weight` variable to force it onto the stack, and avoid the excess
precision. Define `stack_float_t` in `MathExtras.h` for this purpose,
and use it.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Fixes #99396

The result of `VirtRegAuxInfo::weightCalcHelper` can be influenced by
x87 excess precision, which can result in slightly different register
choices when the compiler is hosted on x86_64 or i386. This leads to
different object file output when cross-compiling to i386, or native.

Similar to 7af3432e22b0, we need to add a `volatile` qualifier to the
local `Weight` variable to force it onto the stack, and avoid the excess
precision. Define `stack_float_t` in `MathExtras.h` for this purpose,
and use it.
</pre>
</div>
</content>
</entry>
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