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<title>llvm-project.git/llvm/lib/CodeGen/BreakFalseDeps.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>CodeGen: Remove TRI argument from getRegClass (#158225)</title>
<updated>2025-11-10T23:43:55+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-10T23:43:55+00:00</published>
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<id>55422e804b3bd2fcb1a330673af40240e359540f</id>
<content type='text'>
TargetInstrInfo now directly holds a reference to TargetRegisterInfo
and does not need TRI passed in anywhere.</content>
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<pre>
TargetInstrInfo now directly holds a reference to TargetRegisterInfo
and does not need TRI passed in anywhere.</pre>
</div>
</content>
</entry>
<entry>
<title>[NFC][LLVM][CodeGen] Namespace related cleanups (#162999)</title>
<updated>2025-10-13T14:54:50+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-10-13T14:54:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=2a4f5b2751efbddd7bfe9818ab9ea57d03a13752'/>
<id>2a4f5b2751efbddd7bfe9818ab9ea57d03a13752</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[CodeGen][NewPM] Port `ReachingDefAnalysis` to new pass manager. (#159572)</title>
<updated>2025-09-19T13:38:34+00:00</updated>
<author>
<name>Mikhail Gudim</name>
<email>mgudim@gmail.com</email>
</author>
<published>2025-09-19T13:38:34+00:00</published>
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<id>562146499c391f72d3bed6d91a80d432af14db49</id>
<content type='text'>
In this commit:
  (1) Added new pass manager support for `ReachingDefAnalysis`.
  (2) Added printer pass.
  (3) Make old pass manager use `ReachingDefInfoWrapperPass`</content>
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<pre>
In this commit:
  (1) Added new pass manager support for `ReachingDefAnalysis`.
  (2) Added printer pass.
  (3) Make old pass manager use `ReachingDefInfoWrapperPass`</pre>
</div>
</content>
</entry>
<entry>
<title>CodeGen: Remove MachineFunction argument from getRegClass (#158188)</title>
<updated>2025-09-12T10:22:02+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-12T10:22:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=7289f2cd0c371b2539faa628ec0eea58fa61892c'/>
<id>7289f2cd0c371b2539faa628ec0eea58fa61892c</id>
<content type='text'>
This is a low level utility to parse the MCInstrInfo and should
not depend on the state of the function.</content>
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<pre>
This is a low level utility to parse the MCInstrInfo and should
not depend on the state of the function.</pre>
</div>
</content>
</entry>
<entry>
<title>[X86][BreakFalseDeps] Using reverse order for undef register selection (#137569)</title>
<updated>2025-06-11T14:08:20+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2025-06-11T14:08:20+00:00</published>
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<id>76e14deb4a6967388a9bf84db2feeac17a30c786</id>
<content type='text'>
BreakFalseDeps picks the best register for undef operands if
instructions have false dependency. The problem is if the instruction is
close to the beginning of the function, ReachingDefAnalysis is over
optimism to the unused registers, which results in collision with
registers just defined in the caller.

This patch changes the selection of undef register in an reverse order,
which reduces the probability of register collisions between caller and
callee. It brings improvement in some of our internal benchmarks with
negligible effect on other benchmarks.</content>
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<pre>
BreakFalseDeps picks the best register for undef operands if
instructions have false dependency. The problem is if the instruction is
close to the beginning of the function, ReachingDefAnalysis is over
optimism to the unused registers, which results in collision with
registers just defined in the caller.

This patch changes the selection of undef register in an reverse order,
which reduces the probability of register collisions between caller and
callee. It brings improvement in some of our internal benchmarks with
negligible effect on other benchmarks.</pre>
</div>
</content>
</entry>
<entry>
<title>[LLVM][CodeGen] Add convenience accessors for MachineFunctionProperties (#140002)</title>
<updated>2025-05-22T15:07:52+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-05-22T15:07:52+00:00</published>
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<id>1fdf02ad5a4ca155017eea22688365a20aab077c</id>
<content type='text'>
Add per-property has&lt;Prop&gt;/set&lt;Prop&gt;/reset&lt;Prop&gt; functions to
MachineFunctionProperties.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add per-property has&lt;Prop&gt;/set&lt;Prop&gt;/reset&lt;Prop&gt; functions to
MachineFunctionProperties.</pre>
</div>
</content>
</entry>
<entry>
<title>[MC] Add MCRegisterInfo::regunits for iteration over register units</title>
<updated>2023-06-16T02:39:50+00:00</updated>
<author>
<name>Sergei Barannikov</name>
<email>barannikov88@gmail.com</email>
</author>
<published>2023-05-21T01:28:33+00:00</published>
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<id>aa2d0fbc30d948dc9ce7d312ae4c56467fa57932</id>
<content type='text'>
Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D152098
</content>
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<pre>
Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D152098
</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Make use of MachineInstr::all_defs and all_uses. NFCI.</title>
<updated>2023-06-01T18:17:34+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-05-24T13:57:23+00:00</published>
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<id>5022fc2ad31b5e3211e2458347c89412b8c5ec1b</id>
<content type='text'>
Differential Revision: https://reviews.llvm.org/D151424
</content>
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<pre>
Differential Revision: https://reviews.llvm.org/D151424
</pre>
</div>
</content>
</entry>
<entry>
<title>[BreakFalseDeps] Respect dead blocks.</title>
<updated>2023-04-21T05:17:04+00:00</updated>
<author>
<name>Serguei Katkov</name>
<email>serguei.katkov@azul.com</email>
</author>
<published>2023-04-14T07:05:03+00:00</published>
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<id>aa5cc39b6df0c35ff48cb9d1a397cb8fe1ba00ee</id>
<content type='text'>
The pass uses ReachingDefAnalysis which has no information about
instructions in dead blocks.
So do not process them.

Reviewed By: pengfei
Differential Revision: https://reviews.llvm.org/D148329
</content>
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<pre>
The pass uses ReachingDefAnalysis which has no information about
instructions in dead blocks.
So do not process them.

Reviewed By: pengfei
Differential Revision: https://reviews.llvm.org/D148329
</pre>
</div>
</content>
</entry>
<entry>
<title>Fix uninitialized pointer members in CodeGen</title>
<updated>2023-04-17T08:32:46+00:00</updated>
<author>
<name>Akshay Khadse</name>
<email>akshayskhadse@gmail.com</email>
</author>
<published>2023-04-17T08:16:23+00:00</published>
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<id>8bf7f86d7966ff835967669fb6bf23897e20b71d</id>
<content type='text'>
This change initializes the members TSI, LI, DT, PSI, and ORE pointer feilds of the SelectOptimize class to nullptr.

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D148303
</content>
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<pre>
This change initializes the members TSI, LI, DT, PSI, and ORE pointer feilds of the SelectOptimize class to nullptr.

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D148303
</pre>
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</content>
</entry>
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