llvm-project.git/llvm/docs/ReleaseNotes.md, branch users/nico/python-2 Unnamed repository; edit this file 'description' to name the repository. [SHT_LLVM_BB_ADDR_MAP] Remove support for versions 1 and 0 (SHT_LLVM_BB_ADDR_MAP_V0). (#146186) 2025-07-02T17:31:52+00:00 Rahman Lavaee rahmanl@google.com 2025-07-02T17:31:52+00:00 6b623a6622707ea47d84ab0069f766215a6fec44 Version 2 was added more than two years ago (https://github.com/llvm/llvm-project/commit/6015a045d768feab3bae9ad9c0c81e118df8b04a). So it should be safe to deprecate older versions. 
Version 2 was added more than two years ago
(https://github.com/llvm/llvm-project/commit/6015a045d768feab3bae9ad9c0c81e118df8b04a).
So it should be safe to deprecate older versions.
 [llvm][docs] Remove LLDB DWARF64 release note 2025-07-02T14:02:57+00:00 David Spickett david.spickett@linaro.org 2025-07-02T14:02:19+00:00 8b3cc4d1ed06de18166d37e5fb82c68ae4e4a7a4 As a precaution until the issues reported (by me) in https://github.com/llvm/llvm-project/issues/135208 are investigated. 
As a precaution until the issues reported (by me)
in https://github.com/llvm/llvm-project/issues/135208
are investigated.
[lldb] Enable support for DWARF64 format handling (#145645) 2025-07-01T13:05:40+00:00 Hemang Gadhavi hemang.gadhavi@ibm.com 2025-07-01T13:05:40+00:00 da0828b1e93c0fb6266225d8e6d41b2d9ef1f346 This PR introduces support for the DWARF64 format, enabling handling of 64-bit DWARF sections as defined by the DWARF specification. The update includes adjustments to header parsing and modification of form values to accommodate 64-bit offsets and values. Also Added the testcase to verify the DWARF64 format. 
This PR introduces support for the DWARF64 format, enabling handling of
64-bit DWARF sections as defined by the DWARF specification. The update
includes adjustments to header parsing and modification of form values
to accommodate 64-bit offsets and values.
Also Added the testcase to verify the DWARF64 format.
[RISCV] Remove -mattr=+no-rvc-hints (#145138) 2025-06-25T15:24:24+00:00 Craig Topper craig.topper@sifive.com 2025-06-25T15:24:24+00:00 c3b160bcaa7dd5b5564ae8868fb33e7ba6169283 As far as I know binutils does not have a similar option and I don't know of a reason we shouldn't accept the RVC hint instructions. The wording in the spec in the past suggested that maybe these weren't valid instruction names, but that's been modified recently. 
As far as I know binutils does not have a similar option and I don't
know of a reason we shouldn't accept the RVC hint instructions.

The wording in the spec in the past suggested that maybe these
weren't valid instruction names, but that's been modified recently.
 [RISCV] Add Andes AX45MPV processor definition (#145267) 2025-06-24T00:57:55+00:00 Jim Lin jim@andestech.com 2025-06-24T00:57:55+00:00 2f9c97c030c32c1838d7f102d55921ed4d3442e1 Andes AX45MPV is 64-bit in-order dual-issue 8-stage pipeline linux-capable CPU implementing the RV64IMAFDCV ISA extension. That is developed by Andes Technology https://www.andestech.com, a RISC-V IP provider. The overviews for AX45MPV: https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mpv/ Scheduling model for RVV extension will be implemented a follow-up PR. 
Andes AX45MPV is 64-bit in-order dual-issue 8-stage pipeline
linux-capable CPU implementing the RV64IMAFDCV ISA extension. That is
developed by Andes Technology https://www.andestech.com, a RISC-V IP
provider.

The overviews for AX45MPV:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mpv/

Scheduling model for RVV extension will be implemented a follow-up PR.
 [C API] Add getter/setter for samesign flag on icmp (#145247) 2025-06-22T22:05:17+00:00 Benji Smith 6193112+Benjins@users.noreply.github.com 2025-06-22T22:05:17+00:00 8f01edfa112f76050cf812a64f4e9c7baea52375 This was added to the C++ API in https://github.com/llvm/llvm-project/pull/111419 so this change adds accessors in the C API, along with a couple tests. 
This was added to the C++ API in
https://github.com/llvm/llvm-project/pull/111419 so this change adds
accessors in the C API, along with a couple tests.
 [RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension (#144320) 2025-06-18T01:17:46+00:00 Jim Lin jim@andestech.com 2025-06-18T01:17:46+00:00 8ddada41df0488358373cff1d31a47e5ef4961e0 The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. The instructions are similar to `Zvfbfmin` and the only difference with `Zvfbfmin` is that `XAndesVBFHCvt` doesn't have mask variant. 
The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only supports assembler. The instructions are similar to
`Zvfbfmin` and the only difference with `Zvfbfmin` is that
`XAndesVBFHCvt` doesn't have mask variant.
 [symbolizer] Update Release notes. (#142951) 2025-06-06T12:25:07+00:00 Ebuka Ezike yerimyah1@gmail.com 2025-06-06T12:25:07+00:00 89d2d62e4682a32851083a1e32eb64fb7364c39c Also add post-commit changes from commit #71ba852 in PR #135857 --------- Co-authored-by: James Henderson <James.Henderson@sony.com> 
Also add post-commit changes from commit #71ba852

in PR #135857

---------

Co-authored-by: James Henderson <James.Henderson@sony.com>
 [RISCV] Add support for -mtune=andes-45-series (#142900) 2025-06-06T03:34:19+00:00 Jim Lin jim@andestech.com 2025-06-06T03:34:19+00:00 2a8c7d3c693b2e54bee89ee98b3e844cbb97ff6a Enables the use of `-mtune=andes-45-series` to generate code optimized with the Andes 45 series scheduling model and tuning features. 
Enables the use of `-mtune=andes-45-series` to generate code optimized
with the Andes 45 series scheduling model and tuning features.
 [RISCV] Add SiFive X390 processor definition (#142517) 2025-06-04T16:25:59+00:00 Min-Yih Hsu min.hsu@sifive.com 2025-06-04T16:25:59+00:00 feb21e26fa0eff9c977394f04c089ea887f63b9f X390 is an in-order core designed for AI/ML workload, with VLEN=1024. https://www.sifive.com/cores/intelligence-x300-series Scheduling model will be added in a follow-up patch. 
X390 is an in-order core designed for AI/ML workload, with VLEN=1024.
https://www.sifive.com/cores/intelligence-x300-series

Scheduling model will be added in a follow-up patch.