llvm-project.git/llvm/docs/AMDGPUInstructionSyntax.rst, branch users/nico/python-2

[AMDGPU][GFX11][DOC][NFC] Add GFX11 assembler syntax description

2022-12-21T09:49:48+00:00

[AMDGPU][DOC][NFC] Update assembler syntax description

2022-12-20T11:03:46+00:00

Summary of changes:
- Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205).
- Small improvements and clarifications.
- Correct typos.

[AMDGPU][DOC][NFC] Added GFX1030 assembler syntax description

2022-03-25T15:14:04+00:00

[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.

2021-08-27T14:23:20+00:00

Summary of changes:
- Added f16 omod modifier (bug 51386).
- Corrected names of data types (bug 48638).
- Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231).
- Corrected description of integer operands (bug 51130).
- Corrected description of 8-bit DS offsets (bug 51536).
- Improved PERMLANE op_sel description.
- Corrected *SAD* opcode types.

[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.

2020-08-21T11:25:14+00:00

Summary of changes:
- added description of MTBUF instructions and format modifier;
- described limitations of f16 inline constants when used with integer operands;
- updated description of gfx9+ flat global addressing modes;
- v_accvgpr_write_b32 src0 corrections (gfx908);
- minor bugfixing and improvements.

[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description.

2019-07-08T16:50:11+00:00

Summary of changes:
- added description of GFX10;
- added description of operands sccz, vccz, lds_direct, etc;
- minor bugfixing and improvements.

llvm-svn: 365347

[AMDGPU][MC][DOC] A fix for build failure in r349370

2018-12-17T18:53:10+00:00

llvm-svn: 349375

[AMDGPU][MC][DOC] Updated AMD GPU assembler description

2018-12-17T17:38:11+00:00

Stage 2: added detailed description of operands

See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572

llvm-svn: 349368