llvm-project.git/lldb/source/Plugins/Process/Utility/RegisterFlagsDetector_arm64.cpp, branch users/nico/python-2 Unnamed repository; edit this file 'description' to name the repository. [lldb][AArch64] Fix GCS register field detection 2025-01-28T13:50:58+00:00 David Spickett david.spickett@linaro.org 2025-01-28T13:49:24+00:00 0cf6714279d4146ee5d6a5e34195d6fae56ed475 Fixes c5840cc609a3674cf7453a45946f7e4a2a73590b. On platforms where UL is 32 bit, like Windows or 32 bit Linux, this shift was not correct, so we assumed GCS was not present. Use ULL instead, to match the other HWCAP constants. 
Fixes c5840cc609a3674cf7453a45946f7e4a2a73590b.

On platforms where UL is 32 bit, like Windows or 32 bit Linux,
this shift was not correct, so we assumed GCS was not present.

Use ULL instead, to match the other HWCAP constants.
[lldb][AArch64] Add register fields for Guarded Control Stack registers (#124295) 2025-01-28T12:05:24+00:00 David Spickett david.spickett@linaro.org 2025-01-28T12:05:24+00:00 c5840cc609a3674cf7453a45946f7e4a2a73590b The features and locked registers hold the same bits, the latter is a lock for the former. Tested with core files and live processes. I thought about setting a non-zero lock register in the core file, however: * We can be pretty sure it's reading correctly because its between the 2 other GCS registers in the same core file note. * I can't make the test case modify lock bits because userspace can't clear them (without using ptrace) and we don't know what the libc has locked (probably all feature bits). 
The features and locked registers hold the same bits, the latter
is a lock for the former. Tested with core files and live processes.

I thought about setting a non-zero lock register in the core file,
however:
* We can be pretty sure it's reading correctly because its between
  the 2 other GCS registers in the same core file note.
* I can't make the test case modify lock bits because userspace
can't clear them (without using ptrace) and we don't know what the libc
has locked
  (probably all feature bits).
 [lldb][AArch64] Fix crash loading core files on 32 bit systems 2024-09-26T12:06:23+00:00 David Spickett david.spickett@linaro.org 2024-09-26T12:03:28+00:00 3eaaf7c4d062976901c79b523e9f3cc606943119 https://github.com/llvm/llvm-project/pull/109934 added FPMR which uses a bit in hwcaps greater than 31. So it marked the 1 with UL which is fine on 64 bit systems but for 32 bit UL is 4 bytes. Use ULL so we aren't invoking undefined behaviour. 
https://github.com/llvm/llvm-project/pull/109934 added FPMR which
uses a bit in hwcaps greater than 31. So it marked the 1 with UL
which is fine on 64 bit systems but for 32 bit UL is 4 bytes.

Use ULL so we aren't invoking undefined behaviour.
[lldb][AArch64] Add register fields for the fpmr register (#109934) 2024-09-26T10:44:01+00:00 David Spickett david.spickett@linaro.org 2024-09-26T10:44:01+00:00 0e24611f5703d56a93fc2f7e46c73fabf2e3a8fe The FP8 formats have a "_" in the name so that they are: 1. Easier to read. 2. Possible to use in register expressions if/when they are supported. Some other bits do have defined meanings but they are not simple to name. Better that folks read the manual for those. See this page for the full details: https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers/FPMR--Floating-point-Mode-Register 
The FP8 formats have a "_" in the name so that they are:
1. Easier to read.
2. Possible to use in register expressions if/when they are supported.

Some other bits do have defined meanings but they are not simple to
name. Better that folks read the manual for those.

See this page for the full details:

https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers/FPMR--Floating-point-Mode-Register
 [lldb][AArch64] Add register field enum information (#96887) 2024-07-03T07:43:29+00:00 David Spickett david.spickett@linaro.org 2024-07-03T07:43:29+00:00 b77e734e4e6c8f5e016ba3ac49526862e6039482 This enables XML output for enums and adds enums for 2 fields on AArch64 Linux: * mte_ctrl.tcf, which controls how tag faults are delivered. * fpcr.rmode, which sets the rounding mode for floating point operations. The other one we could do is cpsr.btype, but it is not clear what would be useful here so I'm not including it in this change. 
This enables XML output for enums and adds enums for 2 fields on AArch64
Linux:
* mte_ctrl.tcf, which controls how tag faults are delivered.
* fpcr.rmode, which sets the rounding mode for floating point
operations.

The other one we could do is cpsr.btype, but it is not clear what would
be useful here so I'm not including it in this change.
 [lldb][FreeBSD][AArch64] Enable register field detection (#85058) 2024-07-01T15:18:57+00:00 David Spickett david.spickett@linaro.org 2024-07-01T15:18:57+00:00 ea4cf923edf441897c31edd59a0d7bc8c6f380ff This extends the existing register fields support from AArch64 Linux to AArch64 FreeBSD. So you will now see output like this: ``` (lldb) register read cpsr cpsr = 0x60000200 = (N = 0, Z = 1, C = 1, V = 0, DIT = 0, SS = 0, IL = 0, SSBS = 0, D = 1, A = 0, I = 0, F = 0, nRW = 0, EL = 0, SP = 0) ``` Linux and FreeBSD both have HWCAP/HWCAP2 so the detection mechanism is the same and I've renamed the detector class to reflect that. I have confirmed that FreeBSD's treatment of CPSR (spsr as the kernel calls it) is similair enough that we can use the same field information. (see `sys/arm64/include/armreg.h` and `PSR_SETTABLE_64`) For testing I've enabled the same live process test as Linux and added a shell test using an existing FreeBSD core file. Note that the latter does not need XML support because when reading a core file we are not sending the information via target.xml, it's just internal to LLDB. 
This extends the existing register fields support from AArch64 Linux
to AArch64 FreeBSD. So you will now see output like this:
```
(lldb) register read cpsr
    cpsr = 0x60000200
         = (N = 0, Z = 1, C = 1, V = 0, DIT = 0, SS = 0, IL = 0, SSBS = 0, D = 1, A = 0, I = 0, F = 0, nRW = 0, EL = 0, SP = 0) 
```

Linux and FreeBSD both have HWCAP/HWCAP2 so the detection mechanism
is the same and I've renamed the detector class to reflect that.

I have confirmed that FreeBSD's treatment of CPSR (spsr as the kernel
calls it) is similair enough that we can use the same field information.

(see `sys/arm64/include/armreg.h` and `PSR_SETTABLE_64`)

For testing I've enabled the same live process test as Linux
and added a shell test using an existing FreeBSD core file.

Note that the latter does not need XML support because when reading
a core file we are not sending the information via target.xml,
it's just internal to LLDB.