llvm-project.git/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp, branch users/nico/python-2 Unnamed repository; edit this file 'description' to name the repository. [lldb][RISCV] Support optionally disabled FPR for riscv64 (#104547) 2024-09-04T14:31:59+00:00 Alexey Merzlyakov 60094858+AlexeyMerzlyakov@users.noreply.github.com 2024-09-04T14:31:59+00:00 660e34fd38c3fb39fba1871bbf5b2eb3a48bf277 The PR adds the support optionally enabled/disabled FP-registers to LLDB `RegisterInfoPOSIX_riscv64`. This situation might take place for RISC-V builds having no FP-registers, like RV64IMAC or RV64IMACV. To aim this, patch adds `opt_regsets` flags mechanism. It re-works RegisterInfo class to work with flexibly allocated (depending on `opt_regsets` flag) `m_register_sets` and `m_register_infos` vectors instead of statically defined structures. The registration of regsets is being arranged by `m_per_regset_regnum_range` map. The patch flows are spread to `NativeRegisterContextLinux_riscv64` and `RegisterContextCorePOSIX_riscv64` classes, that were tested on: - x86_64 host working with coredumps - RV64GC and RV64IMAC targets working with coredumps and natively in run-time with binaries `EmulateInstructionRISCV` is out of scope of this patch, and its behavior did not change, using maximum set of registers. According testcase built for RV64IMAC (no-FPR) was added to `TestLinuxCore.py`. 
The PR adds the support optionally enabled/disabled FP-registers to LLDB
`RegisterInfoPOSIX_riscv64`. This situation might take place for RISC-V
builds having no FP-registers, like RV64IMAC or RV64IMACV.

To aim this, patch adds `opt_regsets` flags mechanism. It re-works
RegisterInfo class to work with flexibly allocated (depending on
`opt_regsets` flag) `m_register_sets` and `m_register_infos` vectors
instead of statically defined structures. The registration of regsets is
being arranged by `m_per_regset_regnum_range` map.

The patch flows are spread to `NativeRegisterContextLinux_riscv64` and
`RegisterContextCorePOSIX_riscv64` classes, that were tested on:
 - x86_64 host working with coredumps
- RV64GC and RV64IMAC targets working with coredumps and natively in
run-time with binaries

`EmulateInstructionRISCV` is out of scope of this patch, and its
behavior did not change, using maximum set of registers.

According testcase built for RV64IMAC (no-FPR) was added to
`TestLinuxCore.py`.
 [lldb][RISCV] Add RegisterContextPOSIXCore for RISC-V 64 (#93297) 2024-06-05T09:14:48+00:00 Alexey Merzlyakov 60094858+AlexeyMerzlyakov@users.noreply.github.com 2024-06-05T09:14:48+00:00 d3a9043ec2ee7ea278be4f3c86823512e44d01bf The PR adds the support of CoreDump debugging for RISC-V 64. It implements new `RegisterContextCorePOSIX_riscv64` class. Also, the contribution fixes `GetRegisterCount()` -> `GetRegisterSetCount()` misprint in `RegisterContextPOSIX_riscv64::GetRegisterSetCount()` method, which leaded to `set && "Register set should be valid."` assertion during `register info aX` command call. The patch was tested (on coredumps generated for simple Integer/FP calculation code) for _cross x86_64 -> RISCV_ and _native RISCV_ LLDB builds. There were performed basic LLDB functionality tests, such as: - CoreDump file load - Backtrace / frames - GP/FP registers read/info/list - Basic switch between threads - Disassembler code - Memory regions read / display 
The PR adds the support of CoreDump debugging for RISC-V 64. It
implements new `RegisterContextCorePOSIX_riscv64` class.

Also, the contribution fixes `GetRegisterCount()` ->
`GetRegisterSetCount()` misprint in
`RegisterContextPOSIX_riscv64::GetRegisterSetCount()` method, which
leaded to `set && "Register set should be valid."` assertion during
`register info aX` command call.

The patch was tested (on coredumps generated for simple Integer/FP
calculation code) for _cross x86_64 -> RISCV_ and _native RISCV_ LLDB
builds. There were performed basic LLDB functionality tests, such as:

 - CoreDump file load
 - Backtrace / frames
 - GP/FP registers read/info/list
 - Basic switch between threads
 - Disassembler code
 - Memory regions read / display
 [LLDB][RISCV] Add riscv register definition and read/write 2022-08-11T06:24:06+00:00 Emmmer yjhdandan@163.com 2022-08-10T13:36:20+00:00 7bece0f03bf6cbf7f98812b7cff0e789709c9982 This patch is based on the minimal extract of D128250. What is implemented: - Use the same register layout as Linux kernel and mock read/write for `x0` register (the always zero register). - Refactor some duplicate code, and delete unused register definitions. Reviewed By: DavidSpickett Differential Revision: https://reviews.llvm.org/D130342 
This patch is based on the minimal extract of D128250.

What is implemented:
- Use the same register layout as Linux kernel and mock read/write for `x0` register (the always zero register).
- Refactor some duplicate code, and delete unused register definitions.

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D130342