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<title>llvm-project.git/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[LLDB][LoongArch] Add LSX and LASX register definitions and operations</title>
<updated>2025-01-14T01:16:11+00:00</updated>
<author>
<name>wanglei</name>
<email>wanglei@loongson.cn</email>
</author>
<published>2025-01-14T01:16:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=5ea1c873647c02c80556594b9738de6768d98bf1'/>
<id>5ea1c873647c02c80556594b9738de6768d98bf1</id>
<content type='text'>
With this patch, vector registers can be read and written when debugging a live process.

Note: We currently assume that all LoongArch64 processors include the
LSX and LASX extensions.

To add test cases, the following modifications were also made:
lldb/packages/Python/lldbsuite/test/lldbtest.py
lldb/packages/Python/lldbsuite/test/make/Makefile.rules

Reviewed By: DavidSpickett, SixWeining

Pull Request: https://github.com/llvm/llvm-project/pull/120664
</content>
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<pre>
With this patch, vector registers can be read and written when debugging a live process.

Note: We currently assume that all LoongArch64 processors include the
LSX and LASX extensions.

To add test cases, the following modifications were also made:
lldb/packages/Python/lldbsuite/test/lldbtest.py
lldb/packages/Python/lldbsuite/test/make/Makefile.rules

Reviewed By: DavidSpickett, SixWeining

Pull Request: https://github.com/llvm/llvm-project/pull/120664
</pre>
</div>
</content>
</entry>
<entry>
<title>[lldb][LoongArch64] Add support for LoongArch64 in elf-core for lldb (#112296)</title>
<updated>2024-10-21T09:04:55+00:00</updated>
<author>
<name>Liu An</name>
<email>liuan@loongson.cn</email>
</author>
<published>2024-10-21T09:04:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=911a6f2fcc719c46b5b392823473ba0bb5b1f4e1'/>
<id>911a6f2fcc719c46b5b392823473ba0bb5b1f4e1</id>
<content type='text'>
When using the lldb command 'target create --core' on the LoongArch64
architecture, this part of the code is required.</content>
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<pre>
When using the lldb command 'target create --core' on the LoongArch64
architecture, this part of the code is required.</pre>
</div>
</content>
</entry>
<entry>
<title>[LLDB] Add LoongArch register definitions and operations</title>
<updated>2022-11-25T13:19:36+00:00</updated>
<author>
<name>Tiezhu Yang</name>
<email>yangtiezhu@loongson.cn</email>
</author>
<published>2022-11-25T13:18:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=ed34590c1acb300abe51d2686148c62e8c517993'/>
<id>ed34590c1acb300abe51d2686148c62e8c517993</id>
<content type='text'>
Use the same register layout as Linux kernel, implement the
related read and write operations.

Reviewed By: SixWeining, xen0n, DavidSpickett

Differential Revision: https://reviews.llvm.org/D138407
</content>
<content type='xhtml'>
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<pre>
Use the same register layout as Linux kernel, implement the
related read and write operations.

Reviewed By: SixWeining, xen0n, DavidSpickett

Differential Revision: https://reviews.llvm.org/D138407
</pre>
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