llvm-project.git/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp, branch main Unnamed repository; edit this file 'description' to name the repository. [lldb][RISCV] Support optionally disabled FPR for riscv64 (#104547) 2024-09-04T14:31:59+00:00 Alexey Merzlyakov 60094858+AlexeyMerzlyakov@users.noreply.github.com 2024-09-04T14:31:59+00:00 660e34fd38c3fb39fba1871bbf5b2eb3a48bf277 The PR adds the support optionally enabled/disabled FP-registers to LLDB `RegisterInfoPOSIX_riscv64`. This situation might take place for RISC-V builds having no FP-registers, like RV64IMAC or RV64IMACV. To aim this, patch adds `opt_regsets` flags mechanism. It re-works RegisterInfo class to work with flexibly allocated (depending on `opt_regsets` flag) `m_register_sets` and `m_register_infos` vectors instead of statically defined structures. The registration of regsets is being arranged by `m_per_regset_regnum_range` map. The patch flows are spread to `NativeRegisterContextLinux_riscv64` and `RegisterContextCorePOSIX_riscv64` classes, that were tested on: - x86_64 host working with coredumps - RV64GC and RV64IMAC targets working with coredumps and natively in run-time with binaries `EmulateInstructionRISCV` is out of scope of this patch, and its behavior did not change, using maximum set of registers. According testcase built for RV64IMAC (no-FPR) was added to `TestLinuxCore.py`. 
The PR adds the support optionally enabled/disabled FP-registers to LLDB
`RegisterInfoPOSIX_riscv64`. This situation might take place for RISC-V
builds having no FP-registers, like RV64IMAC or RV64IMACV.

To aim this, patch adds `opt_regsets` flags mechanism. It re-works
RegisterInfo class to work with flexibly allocated (depending on
`opt_regsets` flag) `m_register_sets` and `m_register_infos` vectors
instead of statically defined structures. The registration of regsets is
being arranged by `m_per_regset_regnum_range` map.

The patch flows are spread to `NativeRegisterContextLinux_riscv64` and
`RegisterContextCorePOSIX_riscv64` classes, that were tested on:
 - x86_64 host working with coredumps
- RV64GC and RV64IMAC targets working with coredumps and natively in
run-time with binaries

`EmulateInstructionRISCV` is out of scope of this patch, and its
behavior did not change, using maximum set of registers.

According testcase built for RV64IMAC (no-FPR) was added to
`TestLinuxCore.py`.
 [lldb] Turn lldb_private::Status into a value type. (#106163) 2024-08-27T17:59:31+00:00 Adrian Prantl aprantl@apple.com 2024-08-27T17:59:31+00:00 0642cd768b80665585c8500bed2933a3b99123dc This patch removes all of the Set.* methods from Status. This cleanup is part of a series of patches that make it harder use the anti-pattern of keeping a long-lives Status object around and updating it while dropping any errors it contains on the floor. This patch is largely NFC, the more interesting next steps this enables is to: 1. remove Status.Clear() 2. assert that Status::operator=() never overwrites an error 3. remove Status::operator=() Note that step (2) will bring 90% of the benefits for users, and step (3) will dramatically clean up the error handling code in various places. In the end my goal is to convert all APIs that are of the form ` ResultTy DoFoo(Status& error) ` to ` llvm::Expected<ResultTy> DoFoo() ` How to read this patch? The interesting changes are in Status.h and Status.cpp, all other changes are mostly ` perl -pi -e 's/\.SetErrorString/ = Status::FromErrorString/g' $(git grep -l SetErrorString lldb/source) ` plus the occasional manual cleanup. 
This patch removes all of the Set.* methods from Status.

This cleanup is part of a series of patches that make it harder use the
anti-pattern of keeping a long-lives Status object around and updating
it while dropping any errors it contains on the floor.

This patch is largely NFC, the more interesting next steps this enables
is to:
1. remove Status.Clear()
2. assert that Status::operator=() never overwrites an error
3. remove Status::operator=()

Note that step (2) will bring 90% of the benefits for users, and step
(3) will dramatically clean up the error handling code in various
places. In the end my goal is to convert all APIs that are of the form

`    ResultTy DoFoo(Status& error)
`
to

`    llvm::Expected<ResultTy> DoFoo()
`
How to read this patch?

The interesting changes are in Status.h and Status.cpp, all other
changes are mostly

` perl -pi -e 's/\.SetErrorString/ = Status::FromErrorString/g' $(git
grep -l SetErrorString lldb/source)
`
plus the occasional manual cleanup.
 [LLDB] Fix RISCV build 2022-10-25T15:03:16+00:00 Emmmer yjhdandan@163.com 2022-10-25T11:18:24+00:00 c094b1eef08cee93e4dd9e69d0f7f511037c8500 After https://reviews.llvm.org/D135670 Reviewed By: DavidSpickett Differential Revision: https://reviews.llvm.org/D136674 
After https://reviews.llvm.org/D135670

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D136674
[LLDB][RISCV] Fix risc-v target build 2022-08-11T13:42:44+00:00 Emmmer yjhdandan@163.com 2022-08-11T09:12:28+00:00 55e511f9f61992ff57741148a92cd2f6b6a21337 Fixed an inconsistency between D130985 and D130342 This should be a follow-up of D130985 Reviewed By: DavidSpickett Differential Revision: https://reviews.llvm.org/D131667 
Fixed an inconsistency between D130985 and D130342

This should be a follow-up of D130985

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D131667
[LLDB][RISCV] Add riscv register definition and read/write 2022-08-11T06:24:06+00:00 Emmmer yjhdandan@163.com 2022-08-10T13:36:20+00:00 7bece0f03bf6cbf7f98812b7cff0e789709c9982 This patch is based on the minimal extract of D128250. What is implemented: - Use the same register layout as Linux kernel and mock read/write for `x0` register (the always zero register). - Refactor some duplicate code, and delete unused register definitions. Reviewed By: DavidSpickett Differential Revision: https://reviews.llvm.org/D130342 
This patch is based on the minimal extract of D128250.

What is implemented:
- Use the same register layout as Linux kernel and mock read/write for `x0` register (the always zero register).
- Refactor some duplicate code, and delete unused register definitions.

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D130342