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<title>llvm-project.git/clang/test/CodeGenOpenCL/amdgpu-features.cl, branch users/MaskRay/spr/main.elf-orphan-placement-remove-hasinputsections-condition</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[AMDGPU] Add a new target gfx1152 (#94534)</title>
<updated>2024-06-06T16:16:11+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2024-06-06T16:16:11+00:00</published>
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</entry>
<entry>
<title>[test] %clang_cc1 -emit-llvm: remove redundant -S</title>
<updated>2024-05-05T00:00:29+00:00</updated>
<author>
<name>Fangrui Song</name>
<email>i@maskray.me</email>
</author>
<published>2024-05-05T00:00:28+00:00</published>
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<id>c5de4dd1eab00df76c1a68c5f397304ceacb71f2</id>
<content type='text'>
And replace -emit-llvm -o - with -emit-llvm-only
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<pre>
And replace -emit-llvm -o - with -emit-llvm-only
</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Define a feature for v_dot4_f32_* instructions (#84248)</title>
<updated>2024-03-06T22:37:03+00:00</updated>
<author>
<name>Changpeng Fang</name>
<email>changpeng.fang@amd.com</email>
</author>
<published>2024-03-06T22:37:03+00:00</published>
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<content type='text'>
FeatureDot11Insts (dot11-insts) for:
  v_dot4_f32_fp8_fp8, v_dot4_f32_fp8_bf8,
  v_dot4_f32_bf8_fp8, v_dot4_f32_bf8_bf8</content>
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<pre>
FeatureDot11Insts (dot11-insts) for:
  v_dot4_f32_fp8_fp8, v_dot4_f32_fp8_bf8,
  v_dot4_f32_bf8_fp8, v_dot4_f32_bf8_bf8</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (#78414)</title>
<updated>2024-01-24T11:21:15+00:00</updated>
<author>
<name>Mariusz Sikora</name>
<email>mariusz.sikora@amd.com</email>
</author>
<published>2024-01-24T11:21:15+00:00</published>
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<id>cfddb59be2124f7ec615f48a2d0395c6fdb1bb56</id>
<content type='text'>
…bf8 instructions

    Add VOP1, VOP1_DPP8, VOP1_DPP16, VOP3, VOP3_DPP8, VOP3_DPP16
    instructions that were supported on GFX940 (MI300):
    - V_CVT_F32_FP8
    - V_CVT_F32_BF8
    - V_CVT_PK_F32_FP8
    - V_CVT_PK_F32_BF8
    - V_CVT_PK_FP8_F32
    - V_CVT_PK_BF8_F32
    - V_CVT_SR_FP8_F32
    - V_CVT_SR_BF8_F32

---------

Co-authored-by: Mateja Marjanovic &lt;mateja.marjanovic@amd.com&gt;
Co-authored-by: Mirko Brkušanin &lt;Mirko.Brkusanin@amd.com&gt;</content>
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…bf8 instructions

    Add VOP1, VOP1_DPP8, VOP1_DPP16, VOP3, VOP3_DPP8, VOP3_DPP16
    instructions that were supported on GFX940 (MI300):
    - V_CVT_F32_FP8
    - V_CVT_F32_BF8
    - V_CVT_PK_F32_FP8
    - V_CVT_PK_F32_BF8
    - V_CVT_PK_FP8_F32
    - V_CVT_PK_BF8_F32
    - V_CVT_SR_FP8_F32
    - V_CVT_SR_BF8_F32

---------

Co-authored-by: Mateja Marjanovic &lt;mateja.marjanovic@amd.com&gt;
Co-authored-by: Mirko Brkušanin &lt;Mirko.Brkusanin@amd.com&gt;</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Do not emit `V_DOT2C_F32_F16_e32` on GFX12 (#78709)</title>
<updated>2024-01-19T14:36:27+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-01-19T14:36:27+00:00</published>
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<id>ed123880826cd9a4acdcd05409b1fac4203a436a</id>
<content type='text'>
That instruction is not supported on GFX12.
Added a testcase which previously crashed without this change.

Co-authored-by: pvanhout &lt;pierre.vanhoutryve@amd.com&gt;</content>
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<pre>
That instruction is not supported on GFX12.
Added a testcase which previously crashed without this change.

Co-authored-by: pvanhout &lt;pierre.vanhoutryve@amd.com&gt;</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU][GFX12] Add 16 bit atomic fadd instructions (#75917)</title>
<updated>2024-01-18T13:01:09+00:00</updated>
<author>
<name>Mariusz Sikora</name>
<email>mariusz.sikora@amd.com</email>
</author>
<published>2024-01-18T13:01:09+00:00</published>
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<id>3e6589f21c8088d823377b648aaa1a20ec1bc3d5</id>
<content type='text'>
- image_atomic_pk_add_f16
- image_atomic_pk_add_bf16
- ds_pk_add_bf16
- ds_pk_add_f16
- ds_pk_add_rtn_bf16
- ds_pk_add_rtn_f16
- flat_atomic_pk_add_f16
- flat_atomic_pk_add_bf16
- global_atomic_pk_add_f16
- global_atomic_pk_add_bf16
- buffer_atomic_pk_add_f16
- buffer_atomic_pk_add_bf16</content>
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<pre>
- image_atomic_pk_add_f16
- image_atomic_pk_add_bf16
- ds_pk_add_bf16
- ds_pk_add_f16
- ds_pk_add_rtn_bf16
- ds_pk_add_rtn_f16
- flat_atomic_pk_add_f16
- flat_atomic_pk_add_bf16
- global_atomic_pk_add_f16
- global_atomic_pk_add_bf16
- buffer_atomic_pk_add_f16
- buffer_atomic_pk_add_bf16</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU][NFC] Rename feature FP8Insts to FP8ConversionInsts (#78439)</title>
<updated>2024-01-18T07:46:53+00:00</updated>
<author>
<name>Mariusz Sikora</name>
<email>mariusz.sikora@amd.com</email>
</author>
<published>2024-01-18T07:46:53+00:00</published>
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<id>264fd9e13e6006378b2d1de2851b39eec8e98225</id>
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<pre>
</pre>
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</entry>
<entry>
<title>[AMDGPU] Define new targets gfx1200 and gfx1201 (#73133)</title>
<updated>2023-11-23T16:44:05+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-11-23T16:44:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=cf1e0c0b07c09af6b72ee912a5e0529c8ff66cad'/>
<id>cf1e0c0b07c09af6b72ee912a5e0529c8ff66cad</id>
<content type='text'>
Define target names and ELF numbers for new GFX12 targets gfx1200 and
gfx1201. For now they behave identically to GFX11.</content>
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Define target names and ELF numbers for new GFX12 targets gfx1200 and
gfx1201. For now they behave identically to GFX11.</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Add targets gfx1150 and gfx1151</title>
<updated>2023-07-17T12:06:12+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-07-17T08:34:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=92542f2a400024e8a878242afe8231e17df345e5'/>
<id>92542f2a400024e8a878242afe8231e17df345e5</id>
<content type='text'>
This is the target definition only. Currently they are treated the same
as GFX 11.0.x.

Differential Revision: https://reviews.llvm.org/D155429
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<pre>
This is the target definition only. Currently they are treated the same
as GFX 11.0.x.

Differential Revision: https://reviews.llvm.org/D155429
</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Add basic gfx942 target</title>
<updated>2023-05-10T15:51:06+00:00</updated>
<author>
<name>Konstantin Zhuravlyov</name>
<email>kzhuravl_dev@outlook.com</email>
</author>
<published>2023-05-10T15:20:06+00:00</published>
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<id>9d0572797233857397f3fdc35fffcfb490354f56</id>
<content type='text'>
Differential Revision: https://reviews.llvm.org/D149983
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Differential Revision: https://reviews.llvm.org/D149983
</pre>
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