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<title>llvm-project.git, branch users/slinder1/amdgpu-cfi-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>Add MIR test</title>
<updated>2025-11-04T23:05:46+00:00</updated>
<author>
<name>Scott Linder</name>
<email>Scott.Linder@amd.com</email>
</author>
<published>2025-10-24T20:14:48+00:00</published>
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<id>638fa37bcbb86a6645f13c100f1212894226f969</id>
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<pre>
</pre>
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</entry>
<entry>
<title>[MC][Dwarf] Add custom CFI pseudo-ops for use in AMDGPU</title>
<updated>2025-11-04T23:05:46+00:00</updated>
<author>
<name>Emma Pilkington</name>
<email>Emma.Pilkington@amd.com</email>
</author>
<published>2025-06-19T14:59:31+00:00</published>
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<id>9c85e6c801aa59ad279545aca62c8efb3a367849</id>
<content type='text'>
While these can be represented with .cfi_escape, using these pseudo-cfi
instructions makes .s/.mir files more readable, and it is necessary to
support updating registers in CFI instructions (something that the
AMDGPU backend requires).
</content>
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<pre>
While these can be represented with .cfi_escape, using these pseudo-cfi
instructions makes .s/.mir files more readable, and it is necessary to
support updating registers in CFI instructions (something that the
AMDGPU backend requires).
</pre>
</div>
</content>
</entry>
<entry>
<title>[MC] Use a variant to hold MCCFIInstruction state (NFC)</title>
<updated>2025-11-04T23:05:45+00:00</updated>
<author>
<name>Emma Pilkington</name>
<email>Emma.Pilkington@amd.com</email>
</author>
<published>2025-06-19T13:23:22+00:00</published>
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<id>6f6d4345530a8d4d154d287d3ed1c4adc8dbceb4</id>
<content type='text'>
AMDGPU requires more complex CFI rules, normally these would be
expressed with .cfi_escape, however this would make the CFI unreadable
and makes it difficult to update registers in CFI instructions (also
something AMDGPU requires).
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
AMDGPU requires more complex CFI rules, normally these would be
expressed with .cfi_escape, however this would make the CFI unreadable
and makes it difficult to update registers in CFI instructions (also
something AMDGPU requires).
</pre>
</div>
</content>
</entry>
<entry>
<title>[sanitizer_common] Add arm64e module type (#166018)</title>
<updated>2025-11-04T22:32:06+00:00</updated>
<author>
<name>Andrew Haberlandt</name>
<email>ndrewh@users.noreply.github.com</email>
</author>
<published>2025-11-04T22:32:06+00:00</published>
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<id>a51d219ee7ac9ca96ade7639bff5097c8b79c130</id>
<content type='text'>
This will fix some symbolication failures on arm64e machines when the
symbolicator passes the (wrong) architecture string to atos.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This will fix some symbolication failures on arm64e machines when the
symbolicator passes the (wrong) architecture string to atos.</pre>
</div>
</content>
</entry>
<entry>
<title>[libc++] Use saturation builtins directly for {add,sub}_sat (#165228)</title>
<updated>2025-11-04T22:29:13+00:00</updated>
<author>
<name>Nikolas Klauser</name>
<email>nikolasklauser@berlin.de</email>
</author>
<published>2025-11-04T22:29:13+00:00</published>
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<id>d4222bf9e2175dc8d0707442802a222d652d0116</id>
<content type='text'>
This doesn't improve performance (except with optimizations disabled),
since the compiler is able to fold our current implementation. However,
it does significantly reduce the amount of code the compiler has to sift
through, reducing compile times a bit.</content>
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<pre>
This doesn't improve performance (except with optimizations disabled),
since the compiler is able to fold our current implementation. However,
it does significantly reduce the amount of code the compiler has to sift
through, reducing compile times a bit.</pre>
</div>
</content>
</entry>
<entry>
<title>[opt-viewer] Account for optimization records YAML files generated by LTO (#135059)</title>
<updated>2025-11-04T22:03:45+00:00</updated>
<author>
<name>Min-Yih Hsu</name>
<email>min.hsu@sifive.com</email>
</author>
<published>2025-11-04T22:03:45+00:00</published>
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<id>c93df83b0469902ad22de3e98a8325406a96b960</id>
<content type='text'>
The optimization records YAML files generated by Clang's LTO pipeline
are named "\*.opt.ld.yaml" rather than "\*.opt.yaml". This patch adds
that pattern into the search list of `find_opt_files` as well.</content>
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<pre>
The optimization records YAML files generated by Clang's LTO pipeline
are named "\*.opt.ld.yaml" rather than "\*.opt.yaml". This patch adds
that pattern into the search list of `find_opt_files` as well.</pre>
</div>
</content>
</entry>
<entry>
<title>[AArch64] Copy implicit def operands when creating LDP. (#164253)</title>
<updated>2025-11-04T21:55:57+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2025-11-04T21:55:57+00:00</published>
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<id>cf73a0b102c012f30e5ee43638a78ed21e6b81b3</id>
<content type='text'>
Otherwise we might end up with undefined register uses. Copying implicit
uses can cause problems where a register is both defined and used in the
same LDP, so I have not tried to add them here.

Fixes #164230</content>
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<pre>
Otherwise we might end up with undefined register uses. Copying implicit
uses can cause problems where a register is both defined and used in the
same LDP, so I have not tried to add them here.

Fixes #164230</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[mlir][memref]: Collapse strided unit dim even if strides are dynamic" (#166448)</title>
<updated>2025-11-04T21:49:46+00:00</updated>
<author>
<name>Han-Chung Wang</name>
<email>hanhan0912@gmail.com</email>
</author>
<published>2025-11-04T21:49:46+00:00</published>
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<id>b21949eb34037aa1811cc55609ab46c577feab63</id>
<content type='text'>
Reverts llvm/llvm-project#157330

The original revision introduces a bug in `isGuaranteedCollapsible`. The
`memref&lt;3x3x1x96xf32, strided&lt;[288, 96, 96, 1], offset: 864&gt;&gt;` is no
longer collapsable with the change. The revision reverts the change to
bring back correct behavior. `stride` should be computed as `96` like
the old behavior in the failed iteration.


https://github.com/llvm/llvm-project/blob/92a1eb37122fa24e3045fbabdea2bf87127cace5/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp#L2597-L2605</content>
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<pre>
Reverts llvm/llvm-project#157330

The original revision introduces a bug in `isGuaranteedCollapsible`. The
`memref&lt;3x3x1x96xf32, strided&lt;[288, 96, 96, 1], offset: 864&gt;&gt;` is no
longer collapsable with the change. The revision reverts the change to
bring back correct behavior. `stride` should be computed as `96` like
the old behavior in the failed iteration.


https://github.com/llvm/llvm-project/blob/92a1eb37122fa24e3045fbabdea2bf87127cace5/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp#L2597-L2605</pre>
</div>
</content>
</entry>
<entry>
<title>[LoopFusion] Forget loop and block dispositions after latch merge (#166233)</title>
<updated>2025-11-04T21:48:39+00:00</updated>
<author>
<name>Alireza Torabian</name>
<email>alireza.torabian@huawei.com</email>
</author>
<published>2025-11-04T21:48:39+00:00</published>
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<id>025e431e7450cada2724b19eb59354a6c020fa4f</id>
<content type='text'>
Merging the latches of loops may affect the dispositions, so they should
be forgotten after the merge. This patch fixed the crash in loop fusion
[#164082](https://github.com/llvm/llvm-project/issues/164082).</content>
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<pre>
Merging the latches of loops may affect the dispositions, so they should
be forgotten after the merge. This patch fixed the crash in loop fusion
[#164082](https://github.com/llvm/llvm-project/issues/164082).</pre>
</div>
</content>
</entry>
<entry>
<title>AArch64: correct `preserve_most` and `preserve_all` on Windows (#166436)</title>
<updated>2025-11-04T21:40:42+00:00</updated>
<author>
<name>Saleem Abdulrasool</name>
<email>compnerd@compnerd.org</email>
</author>
<published>2025-11-04T21:40:42+00:00</published>
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<id>8cd22447af239206daabb42fc63e2824a1f7fb6e</id>
<content type='text'>
This fixes register information handling for the `preserve_most` and
`preserve_all` calling conventions on Windows ARM64.

The root issue was cascading `if` statements whose behavior depended on
their order. This patch makes the minimal, tactical change needed for
Swift’s two calling conventions, unblocking current work. A broader
refactor to remove the ordering dependency is still desired and will
follow in a subsequent PR.</content>
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<pre>
This fixes register information handling for the `preserve_most` and
`preserve_all` calling conventions on Windows ARM64.

The root issue was cascading `if` statements whose behavior depended on
their order. This patch makes the minimal, tactical change needed for
Swift’s two calling conventions, unblocking current work. A broader
refactor to remove the ordering dependency is still desired and will
follow in a subsequent PR.</pre>
</div>
</content>
</entry>
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