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<title>llvm-project.git, branch users/ro-i/callbr-amdgpu_2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>fix after rebase</title>
<updated>2025-10-30T14:01:58+00:00</updated>
<author>
<name>Robert Imschweiler</name>
<email>robert.imschweiler@amd.com</email>
</author>
<published>2025-10-30T14:01:58+00:00</published>
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<entry>
<title>[AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with basic inline-asm</title>
<updated>2025-10-30T13:38:24+00:00</updated>
<author>
<name>Robert Imschweiler</name>
<email>robert.imschweiler@amd.com</email>
</author>
<published>2025-08-05T15:24:07+00:00</published>
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<id>b208e34edc6b47fbb7520587902b8e4fcd1821bd</id>
<content type='text'>
Finishes adding basic inline-asm callbr support for AMDGPU, started by
https://github.com/llvm/llvm-project/pull/149308.
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<pre>
Finishes adding basic inline-asm callbr support for AMDGPU, started by
https://github.com/llvm/llvm-project/pull/149308.
</pre>
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</content>
</entry>
<entry>
<title>bunch of small changes to fix a number of LIT tests on z/OS (#165567)</title>
<updated>2025-10-30T13:34:14+00:00</updated>
<author>
<name>Sean Perry</name>
<email>perry@ca.ibm.com</email>
</author>
<published>2025-10-30T13:34:14+00:00</published>
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<id>6106b9473d980dcda5c92edd3944882232fa58aa</id>
<content type='text'>
A collection of small changes to get a number of lit tests working on
z/OS.</content>
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A collection of small changes to get a number of lit tests working on
z/OS.</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU][FixIrreducible][UnifyLoopExits] Support callbr with inline-asm (#149308)</title>
<updated>2025-10-30T13:22:42+00:00</updated>
<author>
<name>Robert Imschweiler</name>
<email>robert.imschweiler@amd.com</email>
</author>
<published>2025-10-30T13:22:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=89540114a72594dbf71fbe728ba6c6d1deecfa03'/>
<id>89540114a72594dbf71fbe728ba6c6d1deecfa03</id>
<content type='text'>
First batch of changes to add support for inline-asm callbr for the
AMDGPU backend.</content>
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<pre>
First batch of changes to add support for inline-asm callbr for the
AMDGPU backend.</pre>
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</content>
</entry>
<entry>
<title>[X86] combinePTESTCC - fold PTESTZ(X,SIGNMASK) -&gt; VTESTPD/PSZ(X,X) on AVX targets (#165676)</title>
<updated>2025-10-30T13:17:12+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-10-30T13:17:12+00:00</published>
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<content type='text'>
If the PTEST is just using the ZF result and one of the operands is a
i32/i64 sign mask we can use the TESTPD/PS instructions instead and
avoid the use of an extra constant.

Fixes some codegen identified in #156233</content>
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If the PTEST is just using the ZF result and one of the operands is a
i32/i64 sign mask we can use the TESTPD/PS instructions instead and
avoid the use of an extra constant.

Fixes some codegen identified in #156233</pre>
</div>
</content>
</entry>
<entry>
<title>[CIR] Upstream handling for __builtin_prefetch (Typo Fix) (#165209)</title>
<updated>2025-10-30T12:58:25+00:00</updated>
<author>
<name>Shawn K</name>
<email>kimshawn02@icloud.com</email>
</author>
<published>2025-10-30T12:58:25+00:00</published>
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<id>5c5cef32607235f9c2b20a308ff5720dbb565c82</id>
<content type='text'>
Not sure if this warrants a PR, but I realized there was a typo in a
test filename from my previous PR #164387.</content>
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Not sure if this warrants a PR, but I realized there was a typo in a
test filename from my previous PR #164387.</pre>
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</content>
</entry>
<entry>
<title>Reapply "[HIP][Clang] Remove __AMDGCN_WAVEFRONT_SIZE macros" (#164217)</title>
<updated>2025-10-30T12:42:32+00:00</updated>
<author>
<name>Fabian Ritter</name>
<email>fabian.ritter@amd.com</email>
</author>
<published>2025-10-30T12:42:32+00:00</published>
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<content type='text'>
This reverts commit 78bf682cb9033cf6a5bbc733e062c7b7d825fdaf.

Original PR: #157463
Revert PR: #158566

The relevant buildbots have been updated to a ROCm version that does not
use the macros anymore to avoid the failures.

Implements SWDEV-522062.</content>
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<pre>
This reverts commit 78bf682cb9033cf6a5bbc733e062c7b7d825fdaf.

Original PR: #157463
Revert PR: #158566

The relevant buildbots have been updated to a ROCm version that does not
use the macros anymore to avoid the failures.

Implements SWDEV-522062.</pre>
</div>
</content>
</entry>
<entry>
<title>[X86] Narrow BT/BTC/BTR/BTS compare + RMW patterns on very large integers (#165540)</title>
<updated>2025-10-30T12:35:39+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-10-30T12:35:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=a55a7207c7e4d98dad32e8d53dd5964ee833edd9'/>
<id>a55a7207c7e4d98dad32e8d53dd5964ee833edd9</id>
<content type='text'>
This patch allows us to narrow single bit-test/twiddle operations for
larger than legal scalar integers to efficiently operate just on the i32
sub-integer block actually affected.

The BITOP(X,SHL(1,IDX)) patterns are split, with the IDX used to access
the specific i32 block as well as specific bit within that block.

BT comparisons are relatively simple, and builds on the truncated
shifted loads fold from #165266.

BTC/BTR/BTS bit twiddling patterns need to match the entire RMW pattern
to safely confirm only one block is affected, but a similar approach is
taken and creates codegen that should allow us to further merge with
matching BT opcodes in a future patch (see #165291).

The resulting codegen is notably more efficient than the heavily
micro-coded memory folded variants of BT/BTC/BTR/BTS.

There is still some work to improve the bit insert 'init' patterns
included in bittest-big-integer.ll but I'm expecting this to be a
straightforward future extension.

Fixes #164225</content>
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This patch allows us to narrow single bit-test/twiddle operations for
larger than legal scalar integers to efficiently operate just on the i32
sub-integer block actually affected.

The BITOP(X,SHL(1,IDX)) patterns are split, with the IDX used to access
the specific i32 block as well as specific bit within that block.

BT comparisons are relatively simple, and builds on the truncated
shifted loads fold from #165266.

BTC/BTR/BTS bit twiddling patterns need to match the entire RMW pattern
to safely confirm only one block is affected, but a similar approach is
taken and creates codegen that should allow us to further merge with
matching BT opcodes in a future patch (see #165291).

The resulting codegen is notably more efficient than the heavily
micro-coded memory folded variants of BT/BTC/BTR/BTS.

There is still some work to improve the bit insert 'init' patterns
included in bittest-big-integer.ll but I'm expecting this to be a
straightforward future extension.

Fixes #164225</pre>
</div>
</content>
</entry>
<entry>
<title>[X86] combinePTESTCC - ensure repeated operands are frozen (#165697)</title>
<updated>2025-10-30T12:30:39+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-10-30T12:30:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=8c8beadcc7542c1481da6378c658d38c98896670'/>
<id>8c8beadcc7542c1481da6378c658d38c98896670</id>
<content type='text'>
As noticed on #165676 - if we're increasing the use of an operand we should freeze it</content>
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As noticed on #165676 - if we're increasing the use of an operand we should freeze it</pre>
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</entry>
<entry>
<title>[llvm-cxxfilt] update docs to reflect #106233 (#165709)</title>
<updated>2025-10-30T12:18:00+00:00</updated>
<author>
<name>Mads Marquart</name>
<email>mads@marquart.dk</email>
</author>
<published>2025-10-30T12:18:00+00:00</published>
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<id>a8656c556610653bfb3dbdf408932da9eca8b8db</id>
<content type='text'>
It looks like the documentation for `llvm-cxxfilt`'s
`--[no-]strip-underscore` options weren't updated when
https://github.com/llvm/llvm-project/pull/106233 was made.

CC @Michael137 (I don't have merge rights myself).</content>
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It looks like the documentation for `llvm-cxxfilt`'s
`--[no-]strip-underscore` options weren't updated when
https://github.com/llvm/llvm-project/pull/106233 was made.

CC @Michael137 (I don't have merge rights myself).</pre>
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