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<title>llvm-project.git, branch users/pcc/spr/main.elf-add-preferred-function-alignment-flag</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[𝘀𝗽𝗿] changes introduced through rebase</title>
<updated>2025-07-18T20:25:54+00:00</updated>
<author>
<name>Peter Collingbourne</name>
<email>peter@pcc.me.uk</email>
</author>
<published>2025-07-18T20:25:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=4f43f0606c3d7e1ce6d069583b5e59f036e112ce'/>
<id>4f43f0606c3d7e1ce6d069583b5e59f036e112ce</id>
<content type='text'>
Created using spr 1.3.6-beta.1

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<pre>
Created using spr 1.3.6-beta.1

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</pre>
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</content>
</entry>
<entry>
<title>[RISCV][IA] Factor out code for extracting operands from mem insts [nfc] (#149344)</title>
<updated>2025-07-18T18:04:18+00:00</updated>
<author>
<name>Philip Reames</name>
<email>preames@rivosinc.com</email>
</author>
<published>2025-07-18T18:04:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=f6641e2f233b809958e4f558f5ad2514bc812cb8'/>
<id>f6641e2f233b809958e4f558f5ad2514bc812cb8</id>
<content type='text'>
We're going to end up repeating the operand extraction four times once
all of the routines have been updated to support both plain load/store
and vp.load/vp.store. I plan to add masked.load/masked.store in the near
future, and we'd need to add that to each of the four cases. Instead,
factor out a single copy of the operand normalization.</content>
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<pre>
We're going to end up repeating the operand extraction four times once
all of the routines have been updated to support both plain load/store
and vp.load/vp.store. I plan to add masked.load/masked.store in the near
future, and we'd need to add that to each of the four cases. Instead,
factor out a single copy of the operand normalization.</pre>
</div>
</content>
</entry>
<entry>
<title>Add section type to support CFI jump table relaxation.</title>
<updated>2025-07-18T17:48:42+00:00</updated>
<author>
<name>Peter Collingbourne</name>
<email>peter@pcc.me.uk</email>
</author>
<published>2025-07-18T17:48:42+00:00</published>
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<id>b5e71d727b6624c160c9186b52d73bdb635770ed</id>
<content type='text'>
For context see main pull request: #147424.

Reviewers: MaskRay

Reviewed By: MaskRay

Pull Request: https://github.com/llvm/llvm-project/pull/149259
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<pre>
For context see main pull request: #147424.

Reviewers: MaskRay

Reviewed By: MaskRay

Pull Request: https://github.com/llvm/llvm-project/pull/149259
</pre>
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</content>
</entry>
<entry>
<title>[ADT] Use a range-based for loop instead of llvm::for_each (NFC) (#149542)</title>
<updated>2025-07-18T17:43:51+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-07-18T17:43:51+00:00</published>
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<id>796d5a89a12407fb0fdf74ea063259b6ca7333d9</id>
<content type='text'>
LLVM Coding Standards discourages llvm::for_each unless we already
have a callable.</content>
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<pre>
LLVM Coding Standards discourages llvm::for_each unless we already
have a callable.</pre>
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</content>
</entry>
<entry>
<title>[mlir][linalg] Allow pack consumer fusion if the tile size is greater than dimension size. (#149438)</title>
<updated>2025-07-18T17:42:42+00:00</updated>
<author>
<name>Han-Chung Wang</name>
<email>hanhan0912@gmail.com</email>
</author>
<published>2025-07-18T17:42:42+00:00</published>
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<content type='text'>
This happens only when you use larger tile size, which is greater than
or equal to the dimension size. In this case, it is a full slice, so it
is fusible.

The IR can be generated during the TileAndFuse process. It is hard to
fix in such driver, so we enable the naive fusion for the case.

---------

Signed-off-by: hanhanW &lt;hanhan0912@gmail.com&gt;</content>
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<pre>
This happens only when you use larger tile size, which is greater than
or equal to the dimension size. In this case, it is a full slice, so it
is fusible.

The IR can be generated during the TileAndFuse process. It is hard to
fix in such driver, so we enable the naive fusion for the case.

---------

Signed-off-by: hanhanW &lt;hanhan0912@gmail.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>[RISCV][IA] Precommit tests for deinterleaveN of masked.load</title>
<updated>2025-07-18T17:39:11+00:00</updated>
<author>
<name>Philip Reames</name>
<email>preames@rivosinc.com</email>
</author>
<published>2025-07-18T17:33:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=87c2adbb589d4cd0b6dfb374fce24d29c6bafac0'/>
<id>87c2adbb589d4cd0b6dfb374fce24d29c6bafac0</id>
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<pre>
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</entry>
<entry>
<title>[mlir][EmitC]Expand the MemRefToEmitC pass - Adding scalars (#148055)</title>
<updated>2025-07-18T17:15:05+00:00</updated>
<author>
<name>Jaden Angella</name>
<email>ajaden@google.com</email>
</author>
<published>2025-07-18T17:15:05+00:00</published>
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<id>7fd91bb6e89be39a130e04058a01d41ae5d600cb</id>
<content type='text'>
This aims to expand the the MemRefToEmitC pass so that it can accept
global scalars.
From:
```
memref.global "private" constant @__constant_xi32 : memref&lt;i32&gt; = dense&lt;-1&gt;
func.func @globals() {
    memref.get_global @__constant_xi32 : memref&lt;i32&gt;
}
```
To:
```
emitc.global static const @__constant_xi32 : i32 = -1
    emitc.func @globals() {
      %0 = get_global @__constant_xi32 : !emitc.lvalue&lt;i32&gt;
      %1 = apply "&amp;"(%0) : (!emitc.lvalue&lt;i32&gt;) -&gt; !emitc.ptr&lt;i32&gt;
      return
    }
```</content>
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<pre>
This aims to expand the the MemRefToEmitC pass so that it can accept
global scalars.
From:
```
memref.global "private" constant @__constant_xi32 : memref&lt;i32&gt; = dense&lt;-1&gt;
func.func @globals() {
    memref.get_global @__constant_xi32 : memref&lt;i32&gt;
}
```
To:
```
emitc.global static const @__constant_xi32 : i32 = -1
    emitc.func @globals() {
      %0 = get_global @__constant_xi32 : !emitc.lvalue&lt;i32&gt;
      %1 = apply "&amp;"(%0) : (!emitc.lvalue&lt;i32&gt;) -&gt; !emitc.ptr&lt;i32&gt;
      return
    }
```</pre>
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</content>
</entry>
<entry>
<title>[SLP][NFC]Add a run line for the test, NFC</title>
<updated>2025-07-18T17:14:18+00:00</updated>
<author>
<name>Alexey Bataev</name>
<email>a.bataev@outlook.com</email>
</author>
<published>2025-07-18T16:51:08+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>[AMDGPU] Add support for `v_sat_pk4_i4_[i8,u8]` on gfx1250 (#149528)</title>
<updated>2025-07-18T17:08:50+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-07-18T17:08:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=2c50e4cac2c50dbbc9eb3ed78bc0178bfa26d23f'/>
<id>2c50e4cac2c50dbbc9eb3ed78bc0178bfa26d23f</id>
<content type='text'>
Co-authored-by: Mekhanoshin, Stanislav &lt;Stanislav.Mekhanoshin@amd.com&gt;
Co-authored-by: Foad, Jay &lt;Jay.Foad@amd.com&gt;</content>
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<pre>
Co-authored-by: Mekhanoshin, Stanislav &lt;Stanislav.Mekhanoshin@amd.com&gt;
Co-authored-by: Foad, Jay &lt;Jay.Foad@amd.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250 (#149518)</title>
<updated>2025-07-18T17:05:08+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-07-18T17:05:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=e11d28faee10dfb5ae6b8aaadadfd2ea1a2a446a'/>
<id>e11d28faee10dfb5ae6b8aaadadfd2ea1a2a446a</id>
<content type='text'>
Co-authored-by: Mekhanoshin, Stanislav &lt;Stanislav.Mekhanoshin@amd.com&gt;</content>
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<pre>
Co-authored-by: Mekhanoshin, Stanislav &lt;Stanislav.Mekhanoshin@amd.com&gt;</pre>
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