Section C3.2.2 (quoted below) in the ARMARM makes this a requirement of
assemblers for load/stores with unscaled offset. It makes no mention of
PRFM so I don't consider this to be a bug, although I can see why we
would want to extend this behaviour to the unscaled variants of these
instructions as well, as GCC does. This patch adds an alias for this.
C3.2.2 Load/store register (unscaled offset)
The load/store register instructions with an unscaled offset support
only one addressing mode:
Base plus an unscaled 9-bit signed immediate offset.
See Load/store addressing modes.
The load/store register (unscaled offset) instructions are required to
disambiguate this instruction class from the load/store register
instruction forms that support an addressing mode of base plus a scaled,
unsigned 12-bit immediate offset, because that can represent some offset
values in the same range.
The ambiguous immediate offsets are byte offsets that are both:
In the range 0-255, inclusive.
Naturally aligned to the access size.
Other byte offsets in the range -256 to 255 inclusive are unambiguous.
An assembler program translating a load/store instruction, for example
LDR, is required to encode an unambiguous offset using the unscaled
9-bit offset form, and to encode an ambiguous offset using the scaled
12-bit offset form. A programmer might force the generation of the
unscaled 9-bit form by using one of the mnemonics in Table C.3.21. Arm
recommends that a disassembler outputs all unscaled 9-bit offset forms
using one of these mnemonics, but unambiguous offsets can be output
using a load/store single register mnemonic, for example, LDR.
Fixes #83226.