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<title>llvm-project.git, branch users/gbossu.vector.extract.1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[AArch64][ISel] Subvector extracts can use undef for second EXT input</title>
<updated>2025-08-01T09:23:30+00:00</updated>
<author>
<name>Gaëtan Bossu</name>
<email>gaetan.bossu@arm.com</email>
</author>
<published>2025-07-31T13:07:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=ebcb4929004ae3f08b2ca3d5d246f29aa73600e1'/>
<id>ebcb4929004ae3f08b2ca3d5d246f29aa73600e1</id>
<content type='text'>
This will later allow us to use the SVE2 constructive variant of EXT
without requiring a MOV. That is because that variant of EXT requires
two consecutive Z registers as input. As a consequence, extracting a
subvector from e.g. z2 into z0 would require:
  z3 = MOV z2
  z0 = EXT_ZZI_B { z2, z3 }, idx

With this change, the z3 part of the { z2, z3 } tuple will be marked as
undef, allowing the MOV to be simplified.

We just need to add patterns for EXT_ZZI_B now, currently only the the
destructive EXT_ZZI variant is selected.
</content>
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<pre>
This will later allow us to use the SVE2 constructive variant of EXT
without requiring a MOV. That is because that variant of EXT requires
two consecutive Z registers as input. As a consequence, extracting a
subvector from e.g. z2 into z0 would require:
  z3 = MOV z2
  z0 = EXT_ZZI_B { z2, z3 }, idx

With this change, the z3 part of the { z2, z3 } tuple will be marked as
undef, allowing the MOV to be simplified.

We just need to add patterns for EXT_ZZI_B now, currently only the the
destructive EXT_ZZI variant is selected.
</pre>
</div>
</content>
</entry>
<entry>
<title>[RISCV] Rewrite deinterleave load as vlse optimization as DAG combine (#150049)</title>
<updated>2025-07-29T14:52:39+00:00</updated>
<author>
<name>Philip Reames</name>
<email>preames@rivosinc.com</email>
</author>
<published>2025-07-29T14:52:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=73245b06b3da19ef70e04cf0f0a0d0df1ba82a57'/>
<id>73245b06b3da19ef70e04cf0f0a0d0df1ba82a57</id>
<content type='text'>
This reworks an existing optimization on the fixed vector (shuffle
based) deinterleave lowering into a DAG combine. This has the effect of
making it kick in much more widely - in particular on the deinterleave
intrinsic (i.e. scalable) path, deinterleaveN (without load) lowering,
but also the intrinsic lowering paths.</content>
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<pre>
This reworks an existing optimization on the fixed vector (shuffle
based) deinterleave lowering into a DAG combine. This has the effect of
making it kick in much more widely - in particular on the deinterleave
intrinsic (i.e. scalable) path, deinterleaveN (without load) lowering,
but also the intrinsic lowering paths.</pre>
</div>
</content>
</entry>
<entry>
<title>[SCCP] Extract PredicateInfo handling into separate method (NFC)</title>
<updated>2025-07-29T14:36:33+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2025-07-29T14:16:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=fa6965f722e0573f62e4d1e533dfa5b3a2ce2c4f'/>
<id>fa6965f722e0573f62e4d1e533dfa5b3a2ce2c4f</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[ARM] Use -cost-kind=all for arith-overflow.ll, arith-ssat.ll and arith-usat.ll. NFC</title>
<updated>2025-07-29T14:08:45+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2025-07-29T14:08:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=46526f879f1f8dd62dd1ea4051bdf1ae413d1fdc'/>
<id>46526f879f1f8dd62dd1ea4051bdf1ae413d1fdc</id>
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</content>
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<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>[DSE] Use MemoryLocation API to get lifetime.end size (NFC)</title>
<updated>2025-07-29T13:46:49+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2025-07-29T13:46:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=74001beded5395f3653aac60c84a10dae277b8b7'/>
<id>74001beded5395f3653aac60c84a10dae277b8b7</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[Clang][Driver] Valid `-march` value is not mandatory in AArch64 multilib (#151103)</title>
<updated>2025-07-29T13:43:11+00:00</updated>
<author>
<name>Victor Campos</name>
<email>victor.campos@arm.com</email>
</author>
<published>2025-07-29T13:43:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=910f6ad15abd0c812ba5df73232215bc7533f7d1'/>
<id>910f6ad15abd0c812ba5df73232215bc7533f7d1</id>
<content type='text'>
If a user passed an invalid value to `-march`, an assertion failure
happened in the AArch64 multilib logic.

But an invalid `-march` value is an expected case that should be handled
via error messages.

This patch removes the requirement that the `-march` value must be
valid.</content>
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<pre>
If a user passed an invalid value to `-march`, an assertion failure
happened in the AArch64 multilib logic.

But an invalid `-march` value is an expected case that should be handled
via error messages.

This patch removes the requirement that the `-march` value must be
valid.</pre>
</div>
</content>
</entry>
<entry>
<title>[mlir][spirv]: Add ImageSupport in ABI Lowering (#150996)</title>
<updated>2025-07-29T13:39:36+00:00</updated>
<author>
<name>Jack Frankland</name>
<email>jack.frankland@arm.com</email>
</author>
<published>2025-07-29T13:39:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=8bb3095c24b1636ecd9bedc36186a8d9de9d7274'/>
<id>8bb3095c24b1636ecd9bedc36186a8d9de9d7274</id>
<content type='text'>
Add support for generating shader arguments as global variables in the
SPIR-V module when the argument in question is a SPIR-V image.

Add lit tests to execute the new logic and check global variables are
being generated.

---------

Signed-off-by: Jack Frankland &lt;jack.frankland@arm.com&gt;</content>
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<pre>
Add support for generating shader arguments as global variables in the
SPIR-V module when the argument in question is a SPIR-V image.

Add lit tests to execute the new logic and check global variables are
being generated.

---------

Signed-off-by: Jack Frankland &lt;jack.frankland@arm.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>[M68k][GISel] Fix buildbot failure caused by additional MIFlags (#151147)</title>
<updated>2025-07-29T13:39:10+00:00</updated>
<author>
<name>Fabian Ritter</name>
<email>fabian.ritter@amd.com</email>
</author>
<published>2025-07-29T13:39:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=f73b0d04f39acad00cdad22fb88a440463c84fb6'/>
<id>f73b0d04f39acad00cdad22fb88a440463c84fb6</id>
<content type='text'>
PR #150392 added the nuw flag to some G_PTR_ADD MIR instructions, this
patch updates the tests for the experimental M68k backend to expect
them.

Should fix buildbot failures like
https://lab.llvm.org/buildbot/#/builders/27/builds/13793</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
PR #150392 added the nuw flag to some G_PTR_ADD MIR instructions, this
patch updates the tests for the experimental M68k backend to expect
them.

Should fix buildbot failures like
https://lab.llvm.org/buildbot/#/builders/27/builds/13793</pre>
</div>
</content>
</entry>
<entry>
<title>[OpenCL] Add decls for cl_intel_bfloat16_conversions (#150393)</title>
<updated>2025-07-29T13:14:41+00:00</updated>
<author>
<name>Mészáros Gergely</name>
<email>gergely.meszaros@intel.com</email>
</author>
<published>2025-07-29T13:14:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=b5fe3eb2d17b711fded1a8c2fbd05a9e4dc06a7f'/>
<id>b5fe3eb2d17b711fded1a8c2fbd05a9e4dc06a7f</id>
<content type='text'>
These map to SPIR-V instructions, which are long supported by the llvm
SPIR-V target [1] and the llvm-spirv translator [2].

Intel's offline compiler (ocloc) and OpenCL implementation trivially
supports these, by having these same declarations [3] and relying on
llvm-spirv to map calls to them to their corresponding SPIR-V
instructions.

[1]:
https://github.com/llvm/llvm-project/blob/531cf8298b08eacdf670bac8c28db97a5dc8cb01/llvm/lib/Target/SPIRV/SPIRVBuiltins.td#L1546C11-L1546C27
[2]:
https://github.com/KhronosGroup/SPIRV-LLVM-Translator/blob/10c7569b3c4cb456fbfdcc86c3de45d46c7f5fa8/lib/SPIRV/OCLUtil.h#L327
[3]:
https://github.com/intel/intel-graphics-compiler/blob/342c4fb729ff6a20a41e19adc8329ad18ba05660/IGC/BiFModule/Languages/OpenCL/opencl_cth_released.h#L6899</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
These map to SPIR-V instructions, which are long supported by the llvm
SPIR-V target [1] and the llvm-spirv translator [2].

Intel's offline compiler (ocloc) and OpenCL implementation trivially
supports these, by having these same declarations [3] and relying on
llvm-spirv to map calls to them to their corresponding SPIR-V
instructions.

[1]:
https://github.com/llvm/llvm-project/blob/531cf8298b08eacdf670bac8c28db97a5dc8cb01/llvm/lib/Target/SPIRV/SPIRVBuiltins.td#L1546C11-L1546C27
[2]:
https://github.com/KhronosGroup/SPIRV-LLVM-Translator/blob/10c7569b3c4cb456fbfdcc86c3de45d46c7f5fa8/lib/SPIRV/OCLUtil.h#L327
[3]:
https://github.com/intel/intel-graphics-compiler/blob/342c4fb729ff6a20a41e19adc8329ad18ba05660/IGC/BiFModule/Languages/OpenCL/opencl_cth_released.h#L6899</pre>
</div>
</content>
</entry>
<entry>
<title>[NFC][WebAssembly] Precommit test for v8i8 mul (#151139)</title>
<updated>2025-07-29T12:49:51+00:00</updated>
<author>
<name>Sam Parker</name>
<email>sam.parker@arm.com</email>
</author>
<published>2025-07-29T12:49:51+00:00</published>
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<id>29e02d792b8cc1bf9017a9ca90b3d9f7cff56fb6</id>
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<pre>
</pre>
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