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<title>llvm-project.git, branch users/Akash/is_device_ptr_lower</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>Fix clang-foramt.</title>
<updated>2025-11-20T14:03:12+00:00</updated>
<author>
<name>Akash Banerjee</name>
<email>Akash.Banerjee@amd.com</email>
</author>
<published>2025-11-20T14:03:12+00:00</published>
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<pre>
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<entry>
<title>Fix test.</title>
<updated>2025-11-20T13:57:31+00:00</updated>
<author>
<name>Akash Banerjee</name>
<email>Akash.Banerjee@amd.com</email>
</author>
<published>2025-11-20T13:57:31+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>move test to flang/test/Lower/OpenMP/target.f90.</title>
<updated>2025-11-20T13:46:34+00:00</updated>
<author>
<name>Akash Banerjee</name>
<email>Akash.Banerjee@amd.com</email>
</author>
<published>2025-11-20T13:46:34+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>[Flang][OpenMP] Add lowering support for is_device_ptr clause</title>
<updated>2025-11-20T13:18:00+00:00</updated>
<author>
<name>Akash Banerjee</name>
<email>Akash.Banerjee@amd.com</email>
</author>
<published>2025-11-20T13:18:00+00:00</published>
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<id>57765c04cd4ec5cd9cf1155126d133c16c6e2252</id>
<content type='text'>
Add support for OpenMP is_device_ptr clause for target directives.
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<pre>
Add support for OpenMP is_device_ptr clause for target directives.
</pre>
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</content>
</entry>
<entry>
<title>[libcxx] Optimize `rng::generate_n` for segmented iterators (#165280)</title>
<updated>2025-10-28T14:22:26+00:00</updated>
<author>
<name>Connector Switch</name>
<email>c8ef@outlook.com</email>
</author>
<published>2025-10-28T14:22:26+00:00</published>
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<id>0621fd0b8837192612d21785ad60664516513cea</id>
<content type='text'>
Part of #102817.

This patch optimizes `rng::generate_n` for segmented iterators by
forwarding the implementation directly to `std::generate_n`.

- before

```
rng::generate_n(deque&lt;int&gt;)/32          21.7 ns         22.0 ns     32000000
rng::generate_n(deque&lt;int&gt;)/50          30.8 ns         30.7 ns     22400000
rng::generate_n(deque&lt;int&gt;)/1024         492 ns          488 ns      1120000
rng::generate_n(deque&lt;int&gt;)/8192        3938 ns         3924 ns       179200
```

- after

```
rng::generate_n(deque&lt;int&gt;)/32          11.0 ns         11.0 ns     64000000
rng::generate_n(deque&lt;int&gt;)/50          16.2 ns         16.1 ns     40727273
rng::generate_n(deque&lt;int&gt;)/1024         292 ns          286 ns      2240000
rng::generate_n(deque&lt;int&gt;)/8192        2291 ns         2302 ns       298667
```</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Part of #102817.

This patch optimizes `rng::generate_n` for segmented iterators by
forwarding the implementation directly to `std::generate_n`.

- before

```
rng::generate_n(deque&lt;int&gt;)/32          21.7 ns         22.0 ns     32000000
rng::generate_n(deque&lt;int&gt;)/50          30.8 ns         30.7 ns     22400000
rng::generate_n(deque&lt;int&gt;)/1024         492 ns          488 ns      1120000
rng::generate_n(deque&lt;int&gt;)/8192        3938 ns         3924 ns       179200
```

- after

```
rng::generate_n(deque&lt;int&gt;)/32          11.0 ns         11.0 ns     64000000
rng::generate_n(deque&lt;int&gt;)/50          16.2 ns         16.1 ns     40727273
rng::generate_n(deque&lt;int&gt;)/1024         292 ns          286 ns      2240000
rng::generate_n(deque&lt;int&gt;)/8192        2291 ns         2302 ns       298667
```</pre>
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</content>
</entry>
<entry>
<title>Bug fixes for ISelLowering for HVX (#164416)</title>
<updated>2025-10-28T14:20:59+00:00</updated>
<author>
<name>Fateme Hosseini</name>
<email>quic_fhossein@quicinc.com</email>
</author>
<published>2025-10-28T14:20:59+00:00</published>
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1. createHvxPrefixPred was computing an invalid byte count for small
predicate types, leading to a crash during instruction selection.
2. HexagonTargetLowering::SplitHvxMemOp assumed the memory vector type
is always simple. This patch adds a guard to avoid processing non-simple
vector types, which can lead to failure.

Patch By:
Fateme Hosseini

Co-authored-by: pavani karveti &lt;quic_pkarveti@quicinc.com&gt;
Co-authored-by: Sergei Larin &lt;slarin@quicinc.com&gt;
Co-authored-by: Pavani Karveti &lt;pkarveti@qti.qualcomm.com&gt;</content>
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<pre>
1. createHvxPrefixPred was computing an invalid byte count for small
predicate types, leading to a crash during instruction selection.
2. HexagonTargetLowering::SplitHvxMemOp assumed the memory vector type
is always simple. This patch adds a guard to avoid processing non-simple
vector types, which can lead to failure.

Patch By:
Fateme Hosseini

Co-authored-by: pavani karveti &lt;quic_pkarveti@quicinc.com&gt;
Co-authored-by: Sergei Larin &lt;slarin@quicinc.com&gt;
Co-authored-by: Pavani Karveti &lt;pkarveti@qti.qualcomm.com&gt;</pre>
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</content>
</entry>
<entry>
<title>[mlir][complex] Fix exp accuracy (#164952)</title>
<updated>2025-10-28T14:01:15+00:00</updated>
<author>
<name>Aleksei Nurmukhametov</name>
<email>anurmukh@amd.com</email>
</author>
<published>2025-10-28T14:01:15+00:00</published>
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<id>d30bd27e7f98c4bf752c50d7189f35ebbf742c3e</id>
<content type='text'>
This ports openxla/stablehlo#2682 implementation by @pearu.

Three tests were added to
`Integration/Dialect/Complex/CPU/correctness.mlir`. I also verified
accuracy using XLA's complex_unary_op_test and its MLIR emitters.</content>
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<pre>
This ports openxla/stablehlo#2682 implementation by @pearu.

Three tests were added to
`Integration/Dialect/Complex/CPU/correctness.mlir`. I also verified
accuracy using XLA's complex_unary_op_test and its MLIR emitters.</pre>
</div>
</content>
</entry>
<entry>
<title>[UTC] Indent switch cases (#165212)</title>
<updated>2025-10-28T14:00:54+00:00</updated>
<author>
<name>Kunqiu Chen</name>
<email>camsyn@foxmail.com</email>
</author>
<published>2025-10-28T14:00:54+00:00</published>
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<id>566c7311d4497ab55db36fcae44579dc244fa4a4</id>
<content type='text'>
LLVM prints switch cases indented by 2 additional spaces, as follows:
```LLVM
  switch i32 %x, label %default [
    i32 0, label %phi
    i32 1, label %phi
  ]
```

Since this only changes the output IR of update_test_checks.py and does
not change the logic of the File Check Pattern, there seems to be no
need to update the existing test cases.</content>
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<pre>
LLVM prints switch cases indented by 2 additional spaces, as follows:
```LLVM
  switch i32 %x, label %default [
    i32 0, label %phi
    i32 1, label %phi
  ]
```

Since this only changes the output IR of update_test_checks.py and does
not change the logic of the File Check Pattern, there seems to be no
need to update the existing test cases.</pre>
</div>
</content>
</entry>
<entry>
<title>[test][DebugInfo] Fix location of test build artifacts (#165349)</title>
<updated>2025-10-28T13:50:51+00:00</updated>
<author>
<name>Jordan Rupprecht</name>
<email>rupprecht@google.com</email>
</author>
<published>2025-10-28T13:50:51+00:00</published>
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<id>29c830cbf8c65fcab7f96f92c8466cbcc9924dd1</id>
<content type='text'>
The test added in #161067 writes artifacts to the current dir, i.e.
`test.o` / `test.dwo` / `test.dwp`, which might not be writeable. Tests
should use `%t` for test artifact location, i.e. `%t.o` / `%t.dwo` /
`%t.dwp` However, since `"test.dwo"` is part of the assembly source file
used as a test input, and that's not something lit will substitute, that
typical approach doesn't work. We can instead ensure the output is in a
good location by running `cd %t` (after setting it up).</content>
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<pre>
The test added in #161067 writes artifacts to the current dir, i.e.
`test.o` / `test.dwo` / `test.dwp`, which might not be writeable. Tests
should use `%t` for test artifact location, i.e. `%t.o` / `%t.dwo` /
`%t.dwp` However, since `"test.dwo"` is part of the assembly source file
used as a test input, and that's not something lit will substitute, that
typical approach doesn't work. We can instead ensure the output is in a
good location by running `cd %t` (after setting it up).</pre>
</div>
</content>
</entry>
<entry>
<title>[NFC][Clang] Regenerate CHECKs - CodeGen/AArch64/neon-across.c</title>
<updated>2025-10-28T13:46:32+00:00</updated>
<author>
<name>Paul Walker</name>
<email>paul.walker@arm.com</email>
</author>
<published>2025-10-28T13:44:57+00:00</published>
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<pre>
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