atomic: Consolidate atomic_read_barrier implementation

All ABIs, except alpha, powerpc, and x86_64, define it to
atomic_full_barrier/__sync_synchronize, which can be mapped to
__atomic_thread_fence (__ATOMIC_SEQ_CST) in most cases, with the
exception of aarch64 (where the acquire fence is generated as
'dmb ishld' instead of 'dmb ish').

For s390x, it defaults to a memory barrier where __sync_synchronize
emits a 'bcr 15,0' (which the manual describes as pipeline
synchronization).

For PowerPC, it allows the use of lwsync for additional chips
(since _ARCH_PWR4 does not cover all chips that support it).

Tested on aarch64-linux-gnu, where the acquire produces a different
instruction that the current code.

Co-authored-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>

5 files changed, 5 insertions, 23 deletions

diff --git a/include/atomic.h b/include/atomic.h
index e289d8a5da..94eb9b582e 100644
--- a/include/atomic.h
+++ b/include/atomic.h
@@ -99,11 +99,6 @@
 #endif
 
 
-#ifndef atomic_read_barrier
-# define atomic_read_barrier() atomic_full_barrier ()
-#endif
-
-
 #ifndef atomic_write_barrier
 # define atomic_write_barrier() atomic_full_barrier ()
 #endif
@@ -259,6 +254,11 @@ void __atomic_link_error (void);
 # define atomic_full_barrier() atomic_thread_fence_seq_cst ()
 #endif
 
+#ifndef atomic_read_barrier
+# define atomic_read_barrier() atomic_thread_fence_acquire ()
+#endif
+
+
 /* ATOMIC_EXCHANGE_USES_CAS is non-zero if atomic_exchange operations
    are implemented based on a CAS loop; otherwise, this is zero and we assume
    that the atomic_exchange operations could provide better performance
diff --git a/sysdeps/alpha/atomic-machine.h b/sysdeps/alpha/atomic-machine.h
index a1d74a930e..198f5dc037 100644
--- a/sysdeps/alpha/atomic-machine.h
+++ b/sysdeps/alpha/atomic-machine.h
@@ -22,5 +22,4 @@
 /* XXX Is this actually correct?  */
 #define ATOMIC_EXCHANGE_USES_CAS 1
 
-#define atomic_read_barrier()	__asm ("mb" : : : "memory");
 #define atomic_write_barrier()	__asm ("wmb" : : : "memory");
diff --git a/sysdeps/generic/malloc-machine.h b/sysdeps/generic/malloc-machine.h
index 195fd8c5e6..4fb8e809cc 100644
--- a/sysdeps/generic/malloc-machine.h
+++ b/sysdeps/generic/malloc-machine.h
@@ -22,10 +22,6 @@
 
 #include <atomic.h>
 
-#ifndef atomic_read_barrier
-# define atomic_read_barrier() atomic_full_barrier ()
-#endif
-
 #ifndef atomic_write_barrier
 # define atomic_write_barrier() atomic_full_barrier ()
 #endif
diff --git a/sysdeps/powerpc/atomic-machine.h b/sysdeps/powerpc/atomic-machine.h
index 65c774a064..e173b61e9c 100644
--- a/sysdeps/powerpc/atomic-machine.h
+++ b/sysdeps/powerpc/atomic-machine.h
@@ -38,22 +38,10 @@
 
 #ifdef _ARCH_PWR4
 /*
- * Newer powerpc64 processors support the new "light weight" sync (lwsync)
- * So if the build is using -mcpu=[power4,power5,power5+,970] we can
- * safely use lwsync.
- */
-# define atomic_read_barrier()	__asm ("lwsync" ::: "memory")
-/*
  * "light weight" sync can also be used for the release barrier.
  */
 # define atomic_write_barrier()	__asm ("lwsync" ::: "memory")
 #else
-/*
- * Older powerpc32 processors don't support the new "light weight"
- * sync (lwsync).  So the only safe option is to use normal sync
- * for all powerpc32 applications.
- */
-# define atomic_read_barrier()	__asm ("sync" ::: "memory")
 # define atomic_write_barrier()	__asm ("sync" ::: "memory")
 #endif
 
diff --git a/sysdeps/x86/atomic-machine.h b/sysdeps/x86/atomic-machine.h
index 97d9c99fa6..f46a0868e3 100644
--- a/sysdeps/x86/atomic-machine.h
+++ b/sysdeps/x86/atomic-machine.h
@@ -31,7 +31,6 @@
 
 #define ATOMIC_EXCHANGE_USES_CAS	0
 
-#define atomic_read_barrier() __asm ("" ::: "memory")
 #define atomic_write_barrier() __asm ("" ::: "memory")
 
 #define atomic_spin_nop() __asm ("pause")