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<title>glibc.git/sysdeps/hppa/atomic-machine.h, branch azanella/atomic-cleanup</title>
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<entry>
<title>nptl: Remove ATOMIC_EXCHANGE_USES_CAS usage</title>
<updated>2025-09-11T17:44:03+00:00</updated>
<author>
<name>Wilco Dijkstra</name>
<email>Wilco.Dijkstra@arm.com</email>
</author>
<published>2025-09-11T11:26:33+00:00</published>
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The only usage was for pthread_spin_lock, introduced by 12d2dd706099aa4,
as a way to optimize the code for certain architectures. Now that atomic
builtins are used by default, let the compiler use the best code sequence
for the atomic exchange.

Co-authored-by: Adhemerval Zanella  &lt;adhemerval.zanella@linaro.org&gt;
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<pre>
The only usage was for pthread_spin_lock, introduced by 12d2dd706099aa4,
as a way to optimize the code for certain architectures. Now that atomic
builtins are used by default, let the compiler use the best code sequence
for the atomic exchange.

Co-authored-by: Adhemerval Zanella  &lt;adhemerval.zanella@linaro.org&gt;
</pre>
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</entry>
<entry>
<title>Define __HAVE_64B_ATOMICS from compiler support</title>
<updated>2025-09-11T17:44:02+00:00</updated>
<author>
<name>Wilco Dijkstra</name>
<email>Wilco.Dijkstra@arm.com</email>
</author>
<published>2025-09-11T11:08:17+00:00</published>
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Now that atomic builtins are used by default, we can rely on the
compiler to define when to use 64-bit atomic operations.

It allows the use of 64-bit atomic operations on some 32-bit ABIs where
they were not previously enabled due to missing pre-processor handling:
hppa, mips64n32, s390, and sparcv9.

Co-authored-by: Adhemerval Zanella  &lt;adhemerval.zanella@linaro.org&gt;
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<pre>
Now that atomic builtins are used by default, we can rely on the
compiler to define when to use 64-bit atomic operations.

It allows the use of 64-bit atomic operations on some 32-bit ABIs where
they were not previously enabled due to missing pre-processor handling:
hppa, mips64n32, s390, and sparcv9.

Co-authored-by: Adhemerval Zanella  &lt;adhemerval.zanella@linaro.org&gt;
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</entry>
<entry>
<title>atomic: Consolidate atomic_full_barrier implementation</title>
<updated>2025-09-11T17:43:46+00:00</updated>
<author>
<name>Adhemerval Zanella</name>
<email>adhemerval.zanella@linaro.org</email>
</author>
<published>2025-09-10T17:22:20+00:00</published>
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All ABIs save for sparcv9 and s390 defines it to __sync_synchronize,
which can be mapped to __atomic_thread_fence (__ATOMIC_SEQ_CST).

For Sparc, it uses a stricter #StoreStore|#LoadStore|#StoreLoad|#LoadLoad
instead of the #StoreLoad generated by __sync_synchronize.

For s390x, it defaults to a memory barrier where __sync_synchronize
emits a 'bcr 15,0' (which the manual describes as pipeline synchronization).

The barrier is used only in one place (pthread_mutex_setprioceiling),
and using a stricter barrier for s390 is ok performance-wise.

Co-authored-by: Wilco Dijkstra &lt;Wilco.Dijkstra@arm.com&gt;
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<pre>
All ABIs save for sparcv9 and s390 defines it to __sync_synchronize,
which can be mapped to __atomic_thread_fence (__ATOMIC_SEQ_CST).

For Sparc, it uses a stricter #StoreStore|#LoadStore|#StoreLoad|#LoadLoad
instead of the #StoreLoad generated by __sync_synchronize.

For s390x, it defaults to a memory barrier where __sync_synchronize
emits a 'bcr 15,0' (which the manual describes as pipeline synchronization).

The barrier is used only in one place (pthread_mutex_setprioceiling),
and using a stricter barrier for s390 is ok performance-wise.

Co-authored-by: Wilco Dijkstra &lt;Wilco.Dijkstra@arm.com&gt;
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</entry>
<entry>
<title>hppa: Move atomic-machine to generic sysdep</title>
<updated>2025-09-11T17:06:43+00:00</updated>
<author>
<name>Adhemerval Zanella</name>
<email>adhemerval.zanella@linaro.org</email>
</author>
<published>2025-09-10T12:05:21+00:00</published>
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There is no Linux specific definitions.
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<pre>
There is no Linux specific definitions.
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