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<title>glibc.git/sysdeps/alpha, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/glibc.git/'/>
<entry>
<title>Revert __HAVE_64B_ATOMICS configure check</title>
<updated>2025-11-14T17:05:20+00:00</updated>
<author>
<name>Adhemerval Zanella</name>
<email>adhemerval.zanella@linaro.org</email>
</author>
<published>2025-11-13T17:26:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/glibc.git/commit/?id=7fec8a5de6826ef9ae440238d698f0fe5a5fb372'/>
<id>7fec8a5de6826ef9ae440238d698f0fe5a5fb372</id>
<content type='text'>
The 53807741fb44edb8e7c094cb5e7d4ff4e92a6ec1 added a configure check
for 64-bit atomic operations that were not previously enabled on some
32-bit ABIs.

However, the NPTL semaphore code casts a sem_t to a new_sem and issues
a 64-bit atomic operation for __HAVE_64B_ATOMICS.  Since sem_t has
32-bit alignment on 32-bit architectures, this prevents the use of
64-bit atomics even if the ABI supports them.

Assume 64-bit atomic support from __WORDSIZE, which maps to how glibc
defines it before the broken change.  Also rename __HAVE_64B_ATOMICS
to USE_64B_ATOMICS to define better the flag meaning.

Checked on x86_64-linux-gnu and i686-linux-gnu.

Reviewed-by: Wilco Dijkstra  &lt;Wilco.Dijkstra@arm.com&gt;
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<pre>
The 53807741fb44edb8e7c094cb5e7d4ff4e92a6ec1 added a configure check
for 64-bit atomic operations that were not previously enabled on some
32-bit ABIs.

However, the NPTL semaphore code casts a sem_t to a new_sem and issues
a 64-bit atomic operation for __HAVE_64B_ATOMICS.  Since sem_t has
32-bit alignment on 32-bit architectures, this prevents the use of
64-bit atomics even if the ABI supports them.

Assume 64-bit atomic support from __WORDSIZE, which maps to how glibc
defines it before the broken change.  Also rename __HAVE_64B_ATOMICS
to USE_64B_ATOMICS to define better the flag meaning.

Checked on x86_64-linux-gnu and i686-linux-gnu.

Reviewed-by: Wilco Dijkstra  &lt;Wilco.Dijkstra@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>math: Remove ldbl-128/s_fma.c</title>
<updated>2025-11-12T18:57:29+00:00</updated>
<author>
<name>Wilco Dijkstra</name>
<email>wilco.dijkstra@arm.com</email>
</author>
<published>2025-11-10T13:52:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/glibc.git/commit/?id=3b7bb7b2f27358f87019af11ef72fbf8e0a5e1f4'/>
<id>3b7bb7b2f27358f87019af11ef72fbf8e0a5e1f4</id>
<content type='text'>
Remove ldbl-128/s_fma.c - it makes no sense to use emulated float128
operations to emulate FMA.  Benchmarking shows dbl-64/s_fma.c is about
twice as fast.  Remove redundant dbl-64/s_fma.c includes in targets
that were trying to work around this issue.

Reviewed-by: Adhemerval Zanella  &lt;adhemerval.zanella@linaro.org&gt;
</content>
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<pre>
Remove ldbl-128/s_fma.c - it makes no sense to use emulated float128
operations to emulate FMA.  Benchmarking shows dbl-64/s_fma.c is about
twice as fast.  Remove redundant dbl-64/s_fma.c includes in targets
that were trying to work around this issue.

Reviewed-by: Adhemerval Zanella  &lt;adhemerval.zanella@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>math: Remove the SVID error handling wrapper from sqrt</title>
<updated>2025-11-04T07:14:01+00:00</updated>
<author>
<name>Adhemerval Zanella</name>
<email>adhemerval.zanella@linaro.org</email>
</author>
<published>2025-10-31T16:08:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/glibc.git/commit/?id=0dfc849eff98812228f3d52af6cb4ad91247711d'/>
<id>0dfc849eff98812228f3d52af6cb4ad91247711d</id>
<content type='text'>
i386 and m68k architectures should use math-use-builtins-sqrt.h rather
than relying on architecture-specific or inline assembly implementations.

The PowerPC optimization for PPC 601/603 (30 years old) is removed.

Tested on x86_64-linux-gnu and i686-linux-gnu.

Reviewed-by: Wilco Dijkstra  &lt;Wilco.Dijkstra@arm.com&gt;
</content>
<content type='xhtml'>
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<pre>
i386 and m68k architectures should use math-use-builtins-sqrt.h rather
than relying on architecture-specific or inline assembly implementations.

The PowerPC optimization for PPC 601/603 (30 years old) is removed.

Tested on x86_64-linux-gnu and i686-linux-gnu.

Reviewed-by: Wilco Dijkstra  &lt;Wilco.Dijkstra@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>nptl: Remove ATOMIC_EXCHANGE_USES_CAS usage</title>
<updated>2025-11-04T07:14:01+00:00</updated>
<author>
<name>Wilco Dijkstra</name>
<email>Wilco.Dijkstra@arm.com</email>
</author>
<published>2025-09-11T13:49:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/glibc.git/commit/?id=324c088a1866f4fec21274c7f8c922258434658f'/>
<id>324c088a1866f4fec21274c7f8c922258434658f</id>
<content type='text'>
The only usage was for pthread_spin_lock, introduced by 12d2dd706099aa4,
as a way to optimize the code for certain architectures. Now that atomic
builtins are used by default, let the compiler use the best code sequence
for the atomic exchange.

Co-authored-by: Adhemerval Zanella  &lt;adhemerval.zanella@linaro.org&gt;
Reviewed-by: Wilco Dijkstra  &lt;Wilco.Dijkstra@arm.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The only usage was for pthread_spin_lock, introduced by 12d2dd706099aa4,
as a way to optimize the code for certain architectures. Now that atomic
builtins are used by default, let the compiler use the best code sequence
for the atomic exchange.

Co-authored-by: Adhemerval Zanella  &lt;adhemerval.zanella@linaro.org&gt;
Reviewed-by: Wilco Dijkstra  &lt;Wilco.Dijkstra@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Define __HAVE_64B_ATOMICS from compiler support</title>
<updated>2025-11-04T07:14:01+00:00</updated>
<author>
<name>Wilco Dijkstra</name>
<email>Wilco.Dijkstra@arm.com</email>
</author>
<published>2025-09-11T13:49:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/glibc.git/commit/?id=53807741fb44edb8e7c094cb5e7d4ff4e92a6ec1'/>
<id>53807741fb44edb8e7c094cb5e7d4ff4e92a6ec1</id>
<content type='text'>
Now that atomic builtins are used by default, we can rely on the
compiler to define when to use 64-bit atomic operations.

It allows the use of 64-bit atomic operations on some 32-bit ABIs where
they were not previously enabled due to missing pre-processor handling:
hppa, mips64n32, s390, and sparcv9.

Co-authored-by: Adhemerval Zanella  &lt;adhemerval.zanella@linaro.org&gt;
Reviewed-by: Uros Bizjak &lt;ubizjak@gmail.com&gt;
Reviewed-by: Wilco Dijkstra  &lt;Wilco.Dijkstra@arm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Now that atomic builtins are used by default, we can rely on the
compiler to define when to use 64-bit atomic operations.

It allows the use of 64-bit atomic operations on some 32-bit ABIs where
they were not previously enabled due to missing pre-processor handling:
hppa, mips64n32, s390, and sparcv9.

Co-authored-by: Adhemerval Zanella  &lt;adhemerval.zanella@linaro.org&gt;
Reviewed-by: Uros Bizjak &lt;ubizjak@gmail.com&gt;
Reviewed-by: Wilco Dijkstra  &lt;Wilco.Dijkstra@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>atomic: Consolidate atomic_read_barrier implementation</title>
<updated>2025-11-04T07:14:01+00:00</updated>
<author>
<name>Adhemerval Zanella</name>
<email>adhemerval.zanella@linaro.org</email>
</author>
<published>2025-09-11T13:49:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/glibc.git/commit/?id=304b22d7f97c23b068d8058986a2afc05da17ffc'/>
<id>304b22d7f97c23b068d8058986a2afc05da17ffc</id>
<content type='text'>
All ABIs, except alpha, powerpc, and x86_64, define it to
atomic_full_barrier/__sync_synchronize, which can be mapped to
__atomic_thread_fence (__ATOMIC_SEQ_CST) in most cases, with the
exception of aarch64 (where the acquire fence is generated as
'dmb ishld' instead of 'dmb ish').

For s390x, it defaults to a memory barrier where __sync_synchronize
emits a 'bcr 15,0' (which the manual describes as pipeline
synchronization).

For PowerPC, it allows the use of lwsync for additional chips
(since _ARCH_PWR4 does not cover all chips that support it).

Tested on aarch64-linux-gnu, where the acquire produces a different
instruction that the current code.

Co-authored-by: Wilco Dijkstra &lt;Wilco.Dijkstra@arm.com&gt;
Reviewed-by: Wilco Dijkstra  &lt;Wilco.Dijkstra@arm.com&gt;
</content>
<content type='xhtml'>
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<pre>
All ABIs, except alpha, powerpc, and x86_64, define it to
atomic_full_barrier/__sync_synchronize, which can be mapped to
__atomic_thread_fence (__ATOMIC_SEQ_CST) in most cases, with the
exception of aarch64 (where the acquire fence is generated as
'dmb ishld' instead of 'dmb ish').

For s390x, it defaults to a memory barrier where __sync_synchronize
emits a 'bcr 15,0' (which the manual describes as pipeline
synchronization).

For PowerPC, it allows the use of lwsync for additional chips
(since _ARCH_PWR4 does not cover all chips that support it).

Tested on aarch64-linux-gnu, where the acquire produces a different
instruction that the current code.

Co-authored-by: Wilco Dijkstra &lt;Wilco.Dijkstra@arm.com&gt;
Reviewed-by: Wilco Dijkstra  &lt;Wilco.Dijkstra@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>atomic: Consolidate atomic_full_barrier implementation</title>
<updated>2025-11-04T07:14:01+00:00</updated>
<author>
<name>Adhemerval Zanella</name>
<email>adhemerval.zanella@linaro.org</email>
</author>
<published>2025-09-11T13:49:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/glibc.git/commit/?id=70ee250fb8b1ea870d5d7e2e7fdf4ea7850efa11'/>
<id>70ee250fb8b1ea870d5d7e2e7fdf4ea7850efa11</id>
<content type='text'>
All ABIs save for sparcv9 and s390 defines it to __sync_synchronize,
which can be mapped to __atomic_thread_fence (__ATOMIC_SEQ_CST).

For Sparc, it uses a stricter #StoreStore|#LoadStore|#StoreLoad|#LoadLoad
instead of the #StoreLoad generated by __sync_synchronize.

For s390x, it defaults to a memory barrier where __sync_synchronize
emits a 'bcr 15,0' (which the manual describes as pipeline synchronization).

The barrier is used only in one place (pthread_mutex_setprioceiling),
and using a stricter barrier for s390 is ok performance-wise.

Co-authored-by: Wilco Dijkstra &lt;Wilco.Dijkstra@arm.com&gt;
Reviewed-by: Wilco Dijkstra  &lt;Wilco.Dijkstra@arm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
All ABIs save for sparcv9 and s390 defines it to __sync_synchronize,
which can be mapped to __atomic_thread_fence (__ATOMIC_SEQ_CST).

For Sparc, it uses a stricter #StoreStore|#LoadStore|#StoreLoad|#LoadLoad
instead of the #StoreLoad generated by __sync_synchronize.

For s390x, it defaults to a memory barrier where __sync_synchronize
emits a 'bcr 15,0' (which the manual describes as pipeline synchronization).

The barrier is used only in one place (pthread_mutex_setprioceiling),
and using a stricter barrier for s390 is ok performance-wise.

Co-authored-by: Wilco Dijkstra &lt;Wilco.Dijkstra@arm.com&gt;
Reviewed-by: Wilco Dijkstra  &lt;Wilco.Dijkstra@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>alpha: Remove USE_ATOMIC_COMPILER_BUILTINS definition</title>
<updated>2025-11-04T07:14:01+00:00</updated>
<author>
<name>Adhemerval Zanella</name>
<email>adhemerval.zanella@linaro.org</email>
</author>
<published>2025-09-11T13:49:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/glibc.git/commit/?id=f6dedc65fd17190d35b776d12d7524b43b629d7d'/>
<id>f6dedc65fd17190d35b776d12d7524b43b629d7d</id>
<content type='text'>
Reviewed-by: Wilco Dijkstra  &lt;Wilco.Dijkstra@arm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Reviewed-by: Wilco Dijkstra  &lt;Wilco.Dijkstra@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>alpha: Fix missing inexact-flag raising for lround/lrint</title>
<updated>2025-09-11T17:48:00+00:00</updated>
<author>
<name>Adhemerval Zanella</name>
<email>adhemerval.zanella@linaro.org</email>
</author>
<published>2025-09-06T22:23:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/glibc.git/commit/?id=dbebe0c4188607991ff2f4deca5707b4afe254f3'/>
<id>dbebe0c4188607991ff2f4deca5707b4afe254f3</id>
<content type='text'>
The l*[rint|round]f implements uses alpha 'cvtst/s', 'addt/suc',
adn 'cvttq/svd' which are not not fully IEEE compliant w.r.t
inexact-flag raising..  Use the software fallback implementation
instead.

Checked on alpha-linux-gnu.

Tested-by: Michael Cree &lt;mcree@orcon.net.nz&gt;
Reviewed-by: Carlos O'Donell &lt;carlos@redhat.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The l*[rint|round]f implements uses alpha 'cvtst/s', 'addt/suc',
adn 'cvttq/svd' which are not not fully IEEE compliant w.r.t
inexact-flag raising..  Use the software fallback implementation
instead.

Checked on alpha-linux-gnu.

Tested-by: Michael Cree &lt;mcree@orcon.net.nz&gt;
Reviewed-by: Carlos O'Donell &lt;carlos@redhat.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>math: Add fetestexcept internal alias</title>
<updated>2025-09-11T17:46:07+00:00</updated>
<author>
<name>Adhemerval Zanella</name>
<email>adhemerval.zanella@linaro.org</email>
</author>
<published>2025-08-25T16:38:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/glibc.git/commit/?id=63ba1a15094c55c26b464b14592a5dbb12595f2f'/>
<id>63ba1a15094c55c26b464b14592a5dbb12595f2f</id>
<content type='text'>
To avoid linknamespace issues on old standards.  It is required
if the fallback fma implementation is used if/when it is also
used internally for other implementation.
Reviewed-by: DJ Delorie &lt;dj@redhat.com&gt;
</content>
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<pre>
To avoid linknamespace issues on old standards.  It is required
if the fallback fma implementation is used if/when it is also
used internally for other implementation.
Reviewed-by: DJ Delorie &lt;dj@redhat.com&gt;
</pre>
</div>
</content>
</entry>
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