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<title>glibc.git/sysdeps/aarch64/fpu/exp2f_advsimd.c, branch master</title>
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<entry>
<title>AArch64: Remove WANT_SIMD_EXCEPT from aarch64 AdvSIMD math routines</title>
<updated>2025-11-18T15:51:15+00:00</updated>
<author>
<name>Dylan Fleming</name>
<email>Dylan.Fleming@arm.com</email>
</author>
<published>2025-11-18T15:34:41+00:00</published>
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<content type='text'>
Remove legacy code for supporting an old Arm Optimised Routines
deprecated feature for throwing SIMD Exceptions.

Reviewed-by: Adhemerval Zanella  &lt;adhemerval.zanella@linaro.org&gt;
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<pre>
Remove legacy code for supporting an old Arm Optimised Routines
deprecated feature for throwing SIMD Exceptions.

Reviewed-by: Adhemerval Zanella  &lt;adhemerval.zanella@linaro.org&gt;
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</entry>
<entry>
<title>Update copyright dates with scripts/update-copyrights</title>
<updated>2025-01-01T19:22:09+00:00</updated>
<author>
<name>Paul Eggert</name>
<email>eggert@cs.ucla.edu</email>
</author>
<published>2025-01-01T18:14:45+00:00</published>
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</entry>
<entry>
<title>AArch64: Improve codegen of AdvSIMD expf family</title>
<updated>2024-12-17T15:28:22+00:00</updated>
<author>
<name>Joana Cruz</name>
<email>Joana.Cruz@arm.com</email>
</author>
<published>2024-12-17T14:50:33+00:00</published>
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<content type='text'>
Load the polynomial evaluation coefficients into 2 vectors and use lanewise MLAs.
Also use intrinsics instead of native operations.
expf: 3% improvement in throughput microbenchmark on Neoverse V1, exp2f: 5%,
exp10f: 13%, coshf: 14%.

Reviewed-by: Wilco Dijkstra  &lt;Wilco.Dijkstra@arm.com&gt;
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Load the polynomial evaluation coefficients into 2 vectors and use lanewise MLAs.
Also use intrinsics instead of native operations.
expf: 3% improvement in throughput microbenchmark on Neoverse V1, exp2f: 5%,
exp10f: 13%, coshf: 14%.

Reviewed-by: Wilco Dijkstra  &lt;Wilco.Dijkstra@arm.com&gt;
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</content>
</entry>
<entry>
<title>Update copyright dates with scripts/update-copyrights</title>
<updated>2024-01-01T18:53:40+00:00</updated>
<author>
<name>Paul Eggert</name>
<email>eggert@cs.ucla.edu</email>
</author>
<published>2024-01-01T18:12:26+00:00</published>
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<entry>
<title>aarch64: Add half-width versions of AdvSIMD f32 libmvec routines</title>
<updated>2023-12-20T08:41:25+00:00</updated>
<author>
<name>Joe Ramsay</name>
<email>Joe.Ramsay@arm.com</email>
</author>
<published>2023-12-19T16:44:01+00:00</published>
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Compilers may emit calls to 'half-width' routines (two-lane
single-precision variants). These have been added in the form of
wrappers around the full-width versions, where the low half of the
vector is simply duplicated. This will perform poorly when one lane
triggers the special-case handler, as there will be a redundant call
to the scalar version, however this is expected to be rare at Ofast.

Reviewed-by: Szabolcs Nagy &lt;szabolcs.nagy@arm.com&gt;
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<pre>
Compilers may emit calls to 'half-width' routines (two-lane
single-precision variants). These have been added in the form of
wrappers around the full-width versions, where the low half of the
vector is simply duplicated. This will perform poorly when one lane
triggers the special-case handler, as there will be a redundant call
to the scalar version, however this is expected to be rare at Ofast.

Reviewed-by: Szabolcs Nagy &lt;szabolcs.nagy@arm.com&gt;
</pre>
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</entry>
<entry>
<title>aarch64: Add vector implementations of exp2 routines</title>
<updated>2023-10-23T14:00:45+00:00</updated>
<author>
<name>Joe Ramsay</name>
<email>Joe.Ramsay@arm.com</email>
</author>
<published>2023-10-05T16:10:49+00:00</published>
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Some routines reuse table from v_exp_data.c
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Some routines reuse table from v_exp_data.c
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