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| author | Jeff Law <jlaw@ventanamicro.com> | 2025-11-13 13:10:12 -0700 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2025-11-13 13:10:12 -0700 |
| commit | 1161fc635450b529159a3804c24d85d94ecb672b (patch) | |
| tree | 3c8296c64db4de4103398b94b5f9db22b4e9075d /libjava/classpath/gnu/java/beans/decoder | |
| parent | 0c69007b1fb98d0fe03d61d81a51e4fc6ac98ce9 (diff) | |
Handle shift-pairs in ext-dce for targets without zero/sign extension insns
This is more prep work for revamping the zero/sign extension patterns on RISC-V
to avoid the need for define_insn_and_splits.
The core issue at hand is for the base ISA we don't have the full set of
sign/zero extensions. So what's been done so far is to pretend we do via a
define_insn_and_split, then split the extensions into shift pairs post-reload
(for the base ISA).
That has multiple undesirable properties, including inhibiting optimization in
some cases and making it harder to add new optimizations in the most natural
way in the future.
The basic approach we've been taking to these problems has been to generate the
desired code at expansion time. When we do that for RISC-V, ext-dce will no
longer see the zero/sign extension nodes when compiling for the base ISA --
instead it'll see shift pairs. And that in turn causes ext-dce to miss
elimination opportunities which is a regression relative to the trunk right
now.
This patch improves ext-dce to recognize the second shift (right) in such a
sequence, then try to match it up with a prior left shift (which has to be the
immediately prior real instruction). When it can pair them up it'll treat the
pair like an extension. The right shift turns into a simple copy of the source
of the left shift.
That prevents optimization regressions with the in flight code to revamp the
zero extension (and then sign extensino) code. No new tests since it's
preventing existing tests from failing to optimize after some in flight stuff
lands.
Bootstrapped and regression tested on x86_64 and tested on all the crosses in
my tester. The Pioneer and BPI will pick it up tonight for bootstrap testing
on RISC-V.
* ext-dce.cc (ext_dce_try_optimize_rshift): New function to optimize a
shift pair implementing a zero/sign extension.
(ext_dce_try_optimize_extension): Renamed from
ext_dce_try_optimize_insn.
(ext_dce_process_uses): Handle shift pairs implementing extensions.
Diffstat (limited to 'libjava/classpath/gnu/java/beans/decoder')
0 files changed, 0 insertions, 0 deletions
