arm: add support for out of range shift amount in MVE asrl and lsll [PR122216]

MVE asrl and lsll instructions have two variants:
- immediate shift amount in the [1..32] range
- shift amount in a register, where negative values reverse the
  direction of the shift

However, RTL assumes that the shift amount is interpreted unsigned, so
we want to make sure undesired simplifications do not take place.
For instance if simplify_rtx optimizes
(set (reg:SI 1) (const_int -5))
(set (reg:DI 2) (ashift:DI (reg:DI 3) (reg:SI 1)))
into:
(set (reg:DI 2) (ashift:DI (reg:DI 3) (const_int -5)))
we do not want this to be interpreted as undefined behavior.

We handle this using a general pattern where:
- immediates are handled by a define_insn_and_split pattern which
  directly maps immediates in [1..32] to the shift operator and splits
  other cases as needed.
- non-immediates are handled by another pattern

gcc/ChangeLog:

	PR target/122216
	* config/arm/arm.md (ashldi3, ashrdi3): Force shift amount into
	QImode.
	* config/arm/constraints.md: Fix comment, Pg is valid in Thumb-2
	state only.
	* config/arm/mve.md (mve_asrl): Handle various shift amount ranges.
	(mve_asrl_imm, mve_asrl_internal): New patterns.
	(mve_lsll): Handle various shift amount ranges.
	(mve_lsll_imm, mve_lsll_internal): New patterns.

gcc/testsuite/ChangeLog:

	PR target/122216
	* gcc.target/arm/mve/intrinsics/asrl-various-ranges.c: New test.
	* gcc.target/arm/mve/intrinsics/lsll-various-ranges.c: New test.

0 files changed, 0 insertions, 0 deletions