diff options
| author | Kees Cook <kees@kernel.org> | 2025-11-21 10:24:34 -0800 |
|---|---|---|
| committer | Andrew Pinski <andrew.pinski@oss.qualcomm.com> | 2025-11-21 19:27:24 -0800 |
| commit | 59a5fecfb260456dd60be687491717f3dbdb354f (patch) | |
| tree | c4c75980f8f94e6c3b53c703e7f313dc72f625ad | |
| parent | 9badb670e28dae8c5a98ac3217eb16dfac20d38c (diff) | |
aarch64: Extract aarch64_indirect_branch_asm for sibcall codegen
Extract indirect branch assembly generation into a new function
aarch64_indirect_branch_asm, paralleling the existing
aarch64_indirect_call_asm function. Replace the open-coded versions in
the sibcall patterns (*sibcall_insn and *sibcall_value_insn) so there
is a common helper for indirect branches where things like SLS mitigation
need to be handled.
gcc/ChangeLog:
* config/aarch64/aarch64-protos.h (aarch64_indirect_branch_asm):
Declare.
* config/aarch64/aarch64.cc (aarch64_indirect_branch_asm): New
function to generate indirect branch with SLS barrier.
* config/aarch64/aarch64.md (*sibcall_insn): Use
aarch64_indirect_branch_asm.
(*sibcall_value_insn): Likewise.
Signed-off-by: Kees Cook <kees@kernel.org>
| -rw-r--r-- | gcc/config/aarch64/aarch64-protos.h | 1 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.cc | 12 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 10 |
3 files changed, 15 insertions, 8 deletions
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index a9e407ba340..68f28bdcae8 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -1272,6 +1272,7 @@ tree aarch64_resolve_overloaded_builtin_general (location_t, tree, void *); const char *aarch64_sls_barrier (int); const char *aarch64_indirect_call_asm (rtx); +extern const char *aarch64_indirect_branch_asm (rtx); extern bool aarch64_harden_sls_retbr_p (void); extern bool aarch64_harden_sls_blr_p (void); diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 6dfdaa4fb9b..89097e23772 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -30822,6 +30822,18 @@ aarch64_indirect_call_asm (rtx addr) return ""; } +/* Generate assembly for AArch64 indirect branch instruction. ADDR is the + target address register. Returns any additional barrier instructions + needed for SLS (Straight Line Speculation) mitigation. */ + +const char * +aarch64_indirect_branch_asm (rtx addr) +{ + gcc_assert (REG_P (addr)); + output_asm_insn ("br\t%0", &addr); + return aarch64_sls_barrier (aarch64_harden_sls_retbr_p ()); +} + /* Emit the assembly instruction to load the thread pointer into DEST. Select between different tpidr_elN registers depending on -mtp= setting. */ diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 855df791bae..de6b1d0ed06 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1581,10 +1581,7 @@ "SIBLING_CALL_P (insn)" { if (which_alternative == 0) - { - output_asm_insn ("br\\t%0", operands); - return aarch64_sls_barrier (aarch64_harden_sls_retbr_p ()); - } + return aarch64_indirect_branch_asm (operands[0]); return "b\\t%c0"; } [(set_attr "type" "branch, branch") @@ -1601,10 +1598,7 @@ "SIBLING_CALL_P (insn)" { if (which_alternative == 0) - { - output_asm_insn ("br\\t%1", operands); - return aarch64_sls_barrier (aarch64_harden_sls_retbr_p ()); - } + return aarch64_indirect_branch_asm (operands[1]); return "b\\t%c1"; } [(set_attr "type" "branch, branch") |