Extract indirect branch assembly generation into a new function
aarch64_indirect_branch_asm, paralleling the existing
aarch64_indirect_call_asm function.  Replace the open-coded versions in
the sibcall patterns (*sibcall_insn and *sibcall_value_insn) so there
is a common helper for indirect branches where things like SLS mitigation
need to be handled.

gcc/ChangeLog:

	* config/aarch64/aarch64-protos.h (aarch64_indirect_branch_asm):
	Declare.
	* config/aarch64/aarch64.cc (aarch64_indirect_branch_asm): New
	function to generate indirect branch with SLS barrier.
	* config/aarch64/aarch64.md (*sibcall_insn): Use
	aarch64_indirect_branch_asm.
	(*sibcall_value_insn): Likewise.

Signed-off-by: Kees Cook <kees@kernel.org>

When laying out arguments of size 0, previously would return the next argument
passing register, without checking that there was a next one.

This was fine for AAPCS as it used R0-R7 for argument passing and R9 would be
occasionally be assigned, but never used.

However, with the introduction of preserve_none PCS there is no obvious "next
register" to use as aaaa dummy value, and so when laying out in the
"next register" when there were no more, an assert triggered an ICE.

This patch fixes this ICE by instead using NULL_RTX for arguments of size 0.

	PR target/122763

gcc/ChangeLog:

	* config/aarch64/aarch64.cc (aarch64_layout_arg): Return NULL_RTX for
	arguments of size 0.
	(aarch64_function_arg_advance): Remove assert.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/pr122763.c: New test.

Support a subset of C/C++ operations (bitwise, conditional etc.) on svbool_t.

gcc/c-family/ChangeLog:

	* c-common.cc (c_build_vec_convert): Support vector boolean
	types for __builtin_convertvector ().

gcc/c/ChangeLog:

	* c-typeck.cc (build_binary_op): Support vector boolean types.

gcc/cp/ChangeLog:

	* typeck.cc (cp_build_binary_op): Likewise.
	* call.cc (build_conditional_expr): Support vector booleans.
	* cvt.cc (ocp_convert): Call target hook to resolve conversion
	between standard and non-standard booleans.

gcc/ChangeLog:

	* config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Make
	SVE vector boolean type equivalent to GNU vectors.
	* config/aarch64/aarch64-sve.md (extend<vpred><mode>2,
	zero_extend<vpred><mode>2, trunc<mode><vpred>2, vec_cmp<mode><mode>):
	New patterns to support additional operations on predicate modes.
	* config/aarch64/aarch64.cc (aarch64_valid_vector_boolean_op): New.
	(aarch64_invalid_unary_op): Consider vector bool types.
	(aarch64_invalid_binary_op): Likewise.
	(aarch64_convert_to_type): Define target hook and handle standard to
	non-standard bool conversion.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/sve/acle/general/cops_bool.c: New.

When applied to a function preserve_none changes the procedure call standard
such that all registers except stack pointer, frame register, and link register
are caller saved. Additionally, it changes the argument passing registers.

	PR target/118328

gcc/ChangeLog:

	* config/aarch64/aarch64.cc (handle_aarch64_vector_pcs_attribute):
	Add handling for ARM_PCS_PRESERVE_NONE.
	(aarch64_pcs_exclusions): New definition.
	(aarch64_gnu_attributes): Add entry for preserve_none and add
	aarch64_pcs_exclusions to aarch64_vector_pcs entry.
	(aarch64_preserve_none_abi): New function.
	(aarch64_fntype_abi): Add handling for preserve_none.
	(aarch64_reg_save_mode): Add handling for ARM_PCS_PRESERVE_NONE.
	(aarch64_hard_regno_call_part_clobbered): Add handling for
	ARM_PCS_PRESERVE_NONE.
	(num_pcs_arg_regs): New helper function.
	(get_pcs_arg_reg): New helper function.
	(aarch64_function_ok_for_sibcall): Add handling for ARM_PCS_PRESERVE_NONE.
	(aarch64_layout_arg): Add preserve_none argument lauout..
	(function_arg_preserve_none_regno_p): New helper function.
	(aarch64_function_arg): Update to handle preserve_none.
	(function_arg_preserve_none_regno_p): Update logic for preserve_none.
	(aarch64_expand_builtin_va_start): Add preserve_none layout.
	(aarch64_setup_incoming_varargs): Add preserve_none layout.
	(aarch64_is_variant_pcs): Update for case of ARM_PCS_PRESERVE_NONE.
	(aarch64_comp_type_attributes): Add preserve_none.
	* config/aarch64/aarch64.h (NUM_PRESERVE_NONE_ARG_REGS): New macro.
	(PRESERVE_NONE_REGISTERS): New macro.
	(enum arm_pcs): Add ARM_PCS_PRESERVE_NONE.
	* doc/extend.texi (preserve_none): Add docs for new attribute.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/preserve_none_1.c: New test.
	* gcc.target/aarch64/preserve_none_mingw_1.c: New test.
	* gcc.target/aarch64/preserve_none_2.c: New test.
	* gcc.target/aarch64/preserve_none_3.c: New test.
	* gcc.target/aarch64/preserve_none_4.c: New test.
	* gcc.target/aarch64/preserve_none_5.c: New test.
	* gcc.target/aarch64/preserve_none_6.c: New test.

Add all the missing FMV features from the ACLE.

gcc/ChangeLog:

	* config/aarch64/aarch64-option-extensions.def (dit): New fmv feature.
	(dpb): New fmv feature.
	(dpb2): New fmv feature.
	(memtag): Change to also define an FMV feature.
	(ssbs): Change to also define an FMV feature.
	(bti): New fmv feature.
	* config/aarch64/aarch64.cc (FEAT_SSBS): Add macro.
	(FEAT_MEMTAG): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/fmv_priority.in: Update for new features.
	* gcc.target/aarch64/fmv_priority1.c: Ditto.
	* gcc.target/aarch64/fmv_priority2.c: Ditto.

The version data-structure already stores the versions in a sorted order so
sorting here is unnecessary.

gcc/ChangeLog:

	* config/aarch64/aarch64.cc (dispatch_function_versions): Remove
	unnecessary sorting and data structure.

Reviewed-by: Wilco Dijkstra <wilco.dijkstra@arm.com>

This fixes the versioning rules for aarch64.

Previously this would prioritize the version string with more extensions
specified regardless of the extension.

The ACLE rules are that any two version strings should be ordered by the
highest priority feature that the versions don't have in common.

	PR target/122190

gcc/ChangeLog:

	* config/aarch64/aarch64.cc (compare_feature_masks): Fix version rules.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/pr122190.c: New test

Reviewed-by: Wilco Dijkstra <wilco.dijkstra@arm.com>

This adds the fmv function versions to the targetclone dump.

This is useful for debugging and tests checking function version priority
ordering.

gcc/ChangeLog:

	* config/aarch64/aarch64.cc (aarch64_generate_version_dispatcher_body):
	Dump function versions and the ordering.

Reviewed-by: Wilco Dijkstra <wilco.dijkstra@arm.com>

Hi All,

In the current Binutils we have disabled the feature gating for sysreg
by default and we have introduced a new flag "-menable-sysreg-checking"
to renable some of this checking.

However in GCC, we have disabled the feature gating of sysreg to read/write
intrinsics __arm_[wr]sr* and we have not added any mechanism to check the
feature gating if needed similar to Binutils.

This patch adds the support for the flag "-menable-sysreg-checking" which
renables some of the feature checking of sysreg to read/write intrinsics
__arm_[wr]sr* similar to Binutils.

For inline assembly, sysreg checks are not performed by CC1 and are
instead delegated to the assembler. By default, the assembler does not
perform these checks either. With this patch, the -menable-sysreg-checking
flag passed to the compiler will also be propagated to the assembler,
enabling sysreg checking for inline assembly.

gcc/ChangeLog:

	* config/aarch64/aarch64-elf.h (ASM_SPEC): Update the macro.
	* config/aarch64/aarch64.cc (aarch64_valid_sysreg_name_p):
	Add feature check condition.
	(aarch64_retrieve_sysreg): Likewise.
	* config/aarch64/aarch64.opt (menable-sysreg-checking):
	Define new flag.
	* doc/invoke.texi (menable-sysreg-checking): Document new flag.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/acle/asm-inlined-sysreg-1.c: New test.
	* gcc.target/aarch64/acle/asm-inlined-sysreg-2.c: Likewise.
	* gcc.target/aarch64/acle/rwsr-gated-1.c: Likewise.
	* gcc.target/aarch64/acle/rwsr-gated-2.c: Likewise.
	* lib/target-supports.exp
	(check_effective_target_aarch64_sysreg_guarding_ok): Check
	assembler support of -menable-sysreg-checking flag.

This patch incorporates changes to this file in Binutils since March
2024 (excluding one patch that was already cherry-picked by
Ezra in July 2025).  It includes:
- New system registers in the 2024 and 2025 architecture extensions.
- Updated feature requirements for most system register accessors.
- Removal of registers that were dropped from the architecture.
- Removal of the unnecessary F_ARCHEXT flag.
- Fixed encoding for pmsdsfr_el1.

The updated architecture feature requirements are only relevant when the
new `-menable-sysreg-checking' option is enabled.

gcc/ChangeLog:

	* config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
	* config/aarch64/aarch64.cc (F_ARCHEXT): Delete flag.
	* config/aarch64/aarch64.h
	(AARCH64_FL_AMU): Delete unused macro.
	(AARCH64_FL_SCXTNUM): Ditto.
	(AARCH64_FL_ID_PFR2): Ditto.
	(AARCH64_FL_AIE): Ditto.
	(AARCH64_FL_DEBUGv8p9): Ditto.
	(AARCH64_FL_FGT2): Ditto.
	(AARCH64_FL_PFAR): Ditto.
	(AARCH64_FL_PMUv3_ICNTR): Ditto.
	(AARCH64_FL_PMUv3_SS): Ditto.
	(AARCH64_FL_PMUv3p9): Ditto.
	(AARCH64_FL_S1PIE): Ditto.
	(AARCH64_FL_S1POE): Ditto.
	(AARCH64_FL_S2PIE): Ditto.
	(AARCH64_FL_S2POE): Ditto.
	(AARCH64_FL_SCTLR2): Ditto.
	(AARCH64_FL_SEBEP): Ditto.
	(AARCH64_FL_SPE_FDS): Ditto.
	(AARCH64_FL_TCR2): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/acle/rwsr-armv8p9.c: Fix incorrect encoding.